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Author: VyacheslavLevytskyy

llvm/lib/Target/SPIRV/SPIRVInstrInfo.td

@@ -219,33 +219,11 @@ def OpTypeCooperativeMatrixKHR: Op<4456, (outs TYPE:$res),
 
 // 3.42.7 Constant-Creation Instructions
 
-//def imm_to_i32 : SDNodeXForm<imm, [{
-//return CurDAG->getTargetConstant(
-//  N->getValueAP().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
-//}]>;
-
-//def fimm_to_i64 : SDNodeXForm<imm, [{
-//return CurDAG->getTargetConstant(
-//  N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
-//}]>;
-
-//def gi_bitcast_fimm_to_i64 : GICustomOperandRenderer<"renderFImm64">,
-//  GISDNodeXFormEquiv<fimm_to_i64>;
-
-//def gi_bitcast_imm_to_i32 : GICustomOperandRenderer<"renderImm32">,
-//  GISDNodeXFormEquiv<imm_to_i32>;
-
-//def PseudoConstI: IntImmLeaf<i64, [{ return Imm.getBitWidth() <= 32; }], imm_to_i32>;
-//def PseudoConstF: FPImmLeaf<f64, [{  return true; }], fimm_to_i64>;
-//def ConstPseudoNull: IntImmLeaf<i64, [{ return Imm.isZero(); }]>;
-
 multiclass IntFPImm<bits<16> opCode, string name> {
   def I: Op<opCode, (outs iID:$dst), (ins TYPE:$type, iID:$src, variable_ops),
                   "$dst = "#name#" $type">;
-//, [(set iID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]
   def F: Op<opCode, (outs fID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
                   "$dst = "#name#" $type">;
-//, [(set fID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]
 }
 defm OpConstant: IntFPImm<43, "OpConstant">;
 

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

@@ -2888,9 +2888,9 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
     assert(MI);
     Register GVarVReg = MI->getOperand(0).getReg();
     bool Res = selectGlobalValue(GVarVReg, *MI, Init);
-    // We violate SSA form by inserting OpVariable having a gMIR instruction
-    // %vreg = G_GLOBAL_VALUE @gvar
-    // We need to fix this erasing the duplicated definition.
+    // We violate SSA form by inserting OpVariable and still having a gMIR
+    // instruction %vreg = G_GLOBAL_VALUE @gvar. We need to fix this by erasing
+    // the duplicated definition.
     if (MI->getOpcode() == TargetOpcode::G_GLOBAL_VALUE) {
       GR.invalidateMachineInstr(MI);
       MI->removeFromParent();

llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp

@@ -53,8 +53,6 @@ extern void processInstr(MachineInstr &MI, MachineIRBuilder &MIB,
 
 static bool mayBeInserted(unsigned Opcode) {
   switch (Opcode) {
-  // case TargetOpcode::G_CONSTANT:
-  // case TargetOpcode::G_FCONSTANT:
   case TargetOpcode::G_SMAX:
   case TargetOpcode::G_UMAX:
   case TargetOpcode::G_SMIN:
@@ -105,13 +103,6 @@ static void processNewInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
         Register ResVReg = I.getOperand(0).getReg();
         // Check if the register defined by the instruction is newly generated
         // or already processed
-        /*if (MRI.getRegClassOrNull(ResVReg)) {
-          if (isTypeFoldingSupported(Opcode)) {
-            insertAssignInstr(ResVReg, nullptr, ResVType, GR, MIB, MRI);
-            processInstr(I, MIB, MRI, GR, GR->getSPIRVTypeForVReg(ResVReg));
-          }
-          continue;
-        }*/
         // Check if we have type defined for operands of the new instruction
         bool IsKnownReg = MRI.getRegClassOrNull(ResVReg);
         SPIRVType *ResVType = GR->getSPIRVTypeForVReg(