[GlobalISel] Add multi-way splitting support for wide scalar shifts.

This patch implements direct N-way splitting for wide scalar shifts instead
of recursive binary splitting. For example, an i512 G_SHL can now be split
directly into 8 i64 operations rather than going through i256 -> i128 -> i64.

The main motivation behind this is to alleviate (although not entirely fix)
pathological compile time issues with huge types, like i4224. The problem
we see is that the recursive splitting strategy combined with our messy
artifact combiner ends up with terribly long compiles as tons of intermediate
artifacts are generated, and then attempted to be combined ad-nauseum.

Going directly from the large shifts to the destination types short-circuits
a lot of these issues, but it's still an abuse of the backend and front-ends
should never be doing this sort of thing.

Author: aemerson

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

@@ -364,6 +364,43 @@ class LegalizerHelper {
                                                       LLT HalfTy,
                                                       LLT ShiftAmtTy);
 
+  /// Multi-way shift legalization: directly split wide shifts into target-sized
+  /// parts in a single step, avoiding recursive binary splitting.
+  LLVM_ABI LegalizeResult narrowScalarShiftMultiway(MachineInstr &MI,
+                                                    LLT TargetTy);
+
+  /// Optimized path for constant shift amounts using static indexing.
+  /// Directly calculates which source parts contribute to each output part
+  /// without generating runtime select chains.
+  LLVM_ABI LegalizeResult narrowScalarShiftByConstantMultiway(MachineInstr &MI,
+                                                              const APInt &Amt,
+                                                              LLT TargetTy,
+                                                              LLT ShiftAmtTy);
+
+  struct ShiftParams {
+    Register WordShift;   // Number of complete words to shift
+    Register BitShift;    // Number of bits to shift within words
+    Register InvBitShift; // Complement bit shift (TargetBits - BitShift)
+    Register Zero;        // Zero constant for SHL/LSHR fill
+    Register SignBit;     // Sign extension value for ASHR fill
+  };
+
+  /// Generates a single output part for constant shifts using direct indexing.
+  /// Calculates which source parts contribute and how they're combined.
+  LLVM_ABI Register buildConstantShiftPart(unsigned Opcode, unsigned PartIdx,
+                                           unsigned NumParts,
+                                           ArrayRef<Register> SrcParts,
+                                           const ShiftParams &Params,
+                                           LLT TargetTy, LLT ShiftAmtTy);
+
+  /// Generates a shift part with carry for variable shifts.
+  /// Combines main operand shifted by BitShift with carry bits from adjacent
+  /// operand.
+  LLVM_ABI Register buildVariableShiftPart(unsigned Opcode,
+                                           Register MainOperand,
+                                           Register ShiftAmt, LLT TargetTy,
+                                           Register CarryOperand = Register());
+
   LLVM_ABI LegalizeResult fewerElementsVectorReductions(MachineInstr &MI,
                                                         unsigned TypeIdx,
                                                         LLT NarrowTy);