[Exegesis] CPU selection, when native arch and target mismatch

Author: AnastasiyaChernikova

llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s

@@ -1,4 +1,4 @@
-# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=AMOAND_D -mattr="+a" | FileCheck --check-prefix=AMOAND_D %s
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --benchmark-phase=assemble-measured-code -opcode-name=AMOAND_D -mattr="+a" | FileCheck --check-prefix=AMOAND_D %s
 
 AMOAND_D:      ---
 AMOAND_D-NEXT: mode: latency
@@ -10,7 +10,7 @@ AMOAND_D-NEXT: register_initial_values:
 AMOAND_D-NEXT: - '[[RE01:X[0-9]+]]=0x0'
 AMOAND_D-DAG: ...
 
-# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=AMOADD_W -mattr="+a" | FileCheck --check-prefix=AMOADD_W %s
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --benchmark-phase=assemble-measured-code -opcode-name=AMOADD_W -mattr="+a" | FileCheck --check-prefix=AMOADD_W %s
 
 AMOADD_W:      ---
 AMOADD_W-NEXT: mode: latency
@@ -22,7 +22,7 @@ AMOADD_W-NEXT: register_initial_values:
 AMOADD_W-NEXT: - '[[RE02:X[0-9]+]]=0x0'
 AMOADD_W-DAG: ...
 
-# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=AMOMAXU_D -mattr="+a" | FileCheck --check-prefix=AMOMAXU_D %s
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --benchmark-phase=assemble-measured-code -opcode-name=AMOMAXU_D -mattr="+a" | FileCheck --check-prefix=AMOMAXU_D %s
 
 AMOMAXU_D:      ---
 AMOMAXU_D-NEXT: mode: latency
@@ -34,7 +34,7 @@ AMOMAXU_D-NEXT: register_initial_values:
 AMOMAXU_D-NEXT: - '[[RE03:X[0-9]+]]=0x0'
 AMOMAXU_D-DAG: ...
 
-# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=AMOMIN_W -mattr="+a" | FileCheck --check-prefix=AMOMIN_W %s
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --benchmark-phase=assemble-measured-code -opcode-name=AMOMIN_W -mattr="+a" | FileCheck --check-prefix=AMOMIN_W %s
 
 AMOMIN_W:      ---
 AMOMIN_W-NEXT: mode: latency
@@ -46,7 +46,7 @@ AMOMIN_W-NEXT: register_initial_values:
 AMOMIN_W-NEXT: - '[[RE04:X[0-9]+]]=0x0'
 AMOMIN_W-DAG: ...
 
-# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=AMOXOR_D -mattr="+a" | FileCheck --check-prefix=AMOXOR_D %s
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --benchmark-phase=assemble-measured-code -opcode-name=AMOXOR_D -mattr="+a" | FileCheck --check-prefix=AMOXOR_D %s
 
 AMOXOR_D:      ---
 AMOXOR_D-NEXT: mode: latency

llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s

@@ -1,44 +1,44 @@
-# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_ADDI -mattr=+c | FileCheck --check-prefix=C_ADDI %s
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --benchmark-phase=assemble-measured-code -opcode-name=C_ADDI -mattr=+c | FileCheck --check-prefix=C_ADDI %s
 
 C_ADDI:      ---
 C_ADDI-NEXT: mode: latency
 C_ADDI-NEXT: key:
 C_ADDI-NEXT:   instructions:
 C_ADDI-NEXT:     - 'C_ADDI [[REG01:X[0-9]+]] [[RE02:X[0-9]+]] [[IMM0:i_0x[0-9]+]]'
 
-# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_ADDIW -mattr=+c | FileCheck --check-prefix=C_ADDIW %s
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --benchmark-phase=assemble-measured-code -opcode-name=C_ADDIW -mattr=+c | FileCheck --check-prefix=C_ADDIW %s
 
 C_ADDIW:      ---
 C_ADDIW-NEXT: mode: latency
 C_ADDIW-NEXT: key:
 C_ADDIW-NEXT:   instructions:
 C_ADDIW-NEXT:     - 'C_ADDIW [[REG11:X[0-9]+]] [[RE12:X[0-9]+]] [[IMM1:i_0x[0-9]+]]'
 
-# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_ANDI -mattr=+c | FileCheck --check-prefix=C_ANDI %s
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --benchmark-phase=assemble-measured-code -opcode-name=C_ANDI -mattr=+c | FileCheck --check-prefix=C_ANDI %s
 
 C_ANDI:      ---
 C_ANDI-NEXT: mode: latency
 C_ANDI-NEXT: key:
 C_ANDI-NEXT:   instructions:
 C_ANDI-NEXT:     - 'C_ANDI [[REG31:X[0-9]+]] [[REG32:X[0-9]+]] [[IMM3:i_0x[0-9]+]]'
 
-# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_SLLI -mattr=+c | FileCheck --check-prefix=C_SLLI %s
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --benchmark-phase=assemble-measured-code -opcode-name=C_SLLI -mattr=+c | FileCheck --check-prefix=C_SLLI %s
 
 C_SLLI:      ---
 C_SLLI-NEXT: mode: latency
 C_SLLI-NEXT: key:
 C_SLLI-NEXT:   instructions:
 C_SLLI-NEXT:     - 'C_SLLI [[REG81:X[0-9]+]] [[REG82:X[0-9]+]] [[IMM8:i_0x[0-9]+]]'
 
-# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_SRAI -mattr=+c | FileCheck --check-prefix=C_SRAI %s
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --benchmark-phase=assemble-measured-code -opcode-name=C_SRAI -mattr=+c | FileCheck --check-prefix=C_SRAI %s
 
 C_SRAI:      ---
 C_SRAI-NEXT: mode: latency
 C_SRAI-NEXT: key:
 C_SRAI-NEXT:   instructions:
 C_SRAI-NEXT:     - 'C_SRAI [[REG91:X[0-9]+]] [[REG92:X[0-9]+]] [[IMM9:i_0x[0-9]+]]'
 
-# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_SRLI -mattr=+c | FileCheck --check-prefix=C_SRLI %s
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --benchmark-phase=assemble-measured-code -opcode-name=C_SRLI -mattr=+c | FileCheck --check-prefix=C_SRLI %s
 
 C_SRLI:      ---
 C_SRLI-NEXT: mode: latency

llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s

@@ -1,57 +1,57 @@
-# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu --mcpu=generic -opcode-name=LD 2>&1 | FileCheck --check-prefix=TEST1 %s
+# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu -opcode-name=LD 2>&1 | FileCheck --check-prefix=TEST1 %s
 
 TEST1:      ---
 TEST1-NEXT: mode: latency
 TEST1-NEXT: key:
 TEST1-NEXT:   instructions:
 TEST1-NEXT:     - 'LD X10 X10 i_0x0'
 
-# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu --mcpu=generic -opcode-name=LW 2>&1 | FileCheck --check-prefix=TEST2 %s
+# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu -opcode-name=LW 2>&1 | FileCheck --check-prefix=TEST2 %s
 
 TEST2:      ---
 TEST2-NEXT: mode: latency
 TEST2-NEXT: key:
 TEST2-NEXT:   instructions:
 TEST2-NEXT:     - 'LW X10 X10 i_0x0'
 
-# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu --mcpu=generic -opcode-name=LH 2>&1 | FileCheck --check-prefix=TEST3 %s
+# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu -opcode-name=LH 2>&1 | FileCheck --check-prefix=TEST3 %s
 
 TEST3:      ---
 TEST3-NEXT: mode: latency
 TEST3-NEXT: key:
 TEST3-NEXT:   instructions:
 TEST3-NEXT:     - 'LH X10 X10 i_0x0'
 
-# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu --mcpu=generic -opcode-name=LWU 2>&1 | FileCheck --check-prefix=TEST4 %s
+# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu -opcode-name=LWU 2>&1 | FileCheck --check-prefix=TEST4 %s
 
 TEST4:      ---
 TEST4-NEXT: mode: latency
 TEST4-NEXT: key:
 TEST4-NEXT:   instructions:
 TEST4-NEXT:     - 'LWU X10 X10 i_0x0'
 
-# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu --mcpu=generic -opcode-name=LBU 2>&1 | FileCheck --check-prefix=TEST5 %s
+# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu -opcode-name=LBU 2>&1 | FileCheck --check-prefix=TEST5 %s
 
 TEST5:      ---
 TEST5-NEXT: mode: latency
 TEST5-NEXT: key:
 TEST5-NEXT:   instructions:
 TEST5-NEXT:     - 'LBU X10 X10 i_0x0'
 
-# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu --mcpu=generic -opcode-name=LUI 2>&1 | FileCheck --check-prefix=TEST6 %s
+# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu -opcode-name=LUI 2>&1 | FileCheck --check-prefix=TEST6 %s
 
 TEST6: LUI: No strategy found to make the execution serial
 
 
-# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu --mcpu=generic -opcode-name=LB 2>&1 | FileCheck --check-prefix=TEST7 %s
+# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu -opcode-name=LB 2>&1 | FileCheck --check-prefix=TEST7 %s
 
 TEST7:      ---
 TEST7-NEXT: mode: latency
 TEST7-NEXT: key:
 TEST7-NEXT:   instructions:
 TEST7-NEXT:     - 'LB X10 X10 i_0x0'
 
-# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu --mcpu=generic -mattr=+a -opcode-name=LR_W_RL 2>&1 | FileCheck --check-prefix=TEST8 %s
+# RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -mtriple=riscv64-unknown-linux-gnu -mattr=+a -opcode-name=LR_W_RL 2>&1 | FileCheck --check-prefix=TEST8 %s
 
 TEST8:      ---
 TEST8-NEXT: mode: latency

llvm/test/tools/llvm-exegesis/RISCV/latency-by-opcode-name-FADD_D.s

@@ -1,4 +1,4 @@
-# RUN: llvm-exegesis -mtriple=riscv64-unknown-linux-gnu --mcpu=generic -mode=latency --benchmark-phase=assemble-measured-code -mattr=+d -opcode-name=FADD_D | FileCheck %s
+# RUN: llvm-exegesis -mtriple=riscv64-unknown-linux-gnu -mode=latency --benchmark-phase=assemble-measured-code -mattr=+d -opcode-name=FADD_D | FileCheck %s
 
 CHECK:      ---
 CHECK-NEXT: mode: latency

llvm/tools/llvm-exegesis/lib/LlvmState.cpp

@@ -45,6 +45,12 @@ Expected<LLVMState> LLVMState::Create(std::string TripleName,
   if (CpuName == "native")
     CpuName = std::string(sys::getHostCPUName());
 
+  if (CpuName.empty()) {
+    std::unique_ptr<MCSubtargetInfo> Empty_STI(
+        TheTarget->createMCSubtargetInfo(TripleName, "", ""));
+    CpuName = Empty_STI->getAllProcessorDescriptions().begin()->Key;
+  }
+
   std::unique_ptr<MCSubtargetInfo> STI(
       TheTarget->createMCSubtargetInfo(TripleName, CpuName, ""));
   assert(STI && "Unable to create subtarget info!");

llvm/tools/llvm-exegesis/llvm-exegesis.cpp

@@ -44,6 +44,7 @@
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/TargetParser/Host.h"
+#include "llvm/TargetParser/Triple.h"
 #include <algorithm>
 #include <string>
 
@@ -479,6 +480,12 @@ void benchmarkMain() {
 #endif
   }
 
+  // case for cross generating, when native arch and target mismatch
+  if ((Triple(sys::getProcessTriple()).getArch() !=
+       Triple(TripleName).getArch()) &&
+      (MCPU == "native"))
+    MCPU = "";
+
   InitializeAllExegesisTargets();
 #define LLVM_EXEGESIS(TargetName)                                              \
   LLVMInitialize##TargetName##AsmPrinter();                                    \