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mtrofinmtrofin
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[LTT] Bias branch weights as "expected" when lowering type tests with conditional (#170752)
We expect the type test to succeed.
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3 files changed

+18
-13
lines changed

3 files changed

+18
-13
lines changed

‎llvm/lib/Transforms/IPO/LowerTypeTests.cpp‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,12 +48,14 @@
4848
#include "llvm/IR/IntrinsicInst.h"
4949
#include "llvm/IR/Intrinsics.h"
5050
#include "llvm/IR/LLVMContext.h"
51+
#include "llvm/IR/MDBuilder.h"
5152
#include "llvm/IR/Metadata.h"
5253
#include "llvm/IR/Module.h"
5354
#include "llvm/IR/ModuleSummaryIndex.h"
5455
#include "llvm/IR/ModuleSummaryIndexYAML.h"
5556
#include "llvm/IR/Operator.h"
5657
#include "llvm/IR/PassManager.h"
58+
#include "llvm/IR/ProfDataUtils.h"
5759
#include "llvm/IR/ReplaceConstant.h"
5860
#include "llvm/IR/Type.h"
5961
#include "llvm/IR/Use.h"
@@ -802,7 +804,9 @@ Value *LowerTypeTestsModule::lowerTypeTestCall(Metadata *TypeId, CallInst *CI,
802804
return createBitSetTest(ThenB, TIL, BitOffset);
803805
}
804806

805-
IRBuilder<> ThenB(SplitBlockAndInsertIfThen(OffsetInRange, CI, false));
807+
MDBuilder MDB(M.getContext());
808+
IRBuilder<> ThenB(SplitBlockAndInsertIfThen(OffsetInRange, CI, false,
809+
MDB.createLikelyBranchWeights()));
806810

807811
// Now that we know that the offset is in range and aligned, load the
808812
// appropriate bit from the bitset.

‎llvm/test/Transforms/LowerTypeTests/import.ll‎

Lines changed: 13 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,7 @@ define i1 @bytearray7(ptr %p) {
9292
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray7_global_addr to i64), [[TMP1]]
9393
; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray7_align to i64))
9494
; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
95-
; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
95+
; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]], !prof [[PROF6:![0-9]+]]
9696
; X86: 5:
9797
; X86-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP3]]
9898
; X86-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
@@ -109,7 +109,7 @@ define i1 @bytearray7(ptr %p) {
109109
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray7_global_addr to i64), [[TMP1]]
110110
; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 3)
111111
; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 43
112-
; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
112+
; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]], !prof [[PROF0:![0-9]+]]
113113
; ARM: 5:
114114
; ARM-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP3]]
115115
; ARM-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
@@ -131,7 +131,7 @@ define i1 @bytearray32(ptr %p) {
131131
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray32_global_addr to i64), [[TMP1]]
132132
; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray32_align to i64))
133133
; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_bytearray32_size_m1 to i64)
134-
; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
134+
; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]], !prof [[PROF6]]
135135
; X86: 5:
136136
; X86-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP3]]
137137
; X86-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
@@ -148,7 +148,7 @@ define i1 @bytearray32(ptr %p) {
148148
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray32_global_addr to i64), [[TMP1]]
149149
; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 4)
150150
; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 12346
151-
; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
151+
; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]], !prof [[PROF0]]
152152
; ARM: 5:
153153
; ARM-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP3]]
154154
; ARM-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
@@ -170,7 +170,7 @@ define i1 @inline5(ptr %p) {
170170
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_inline5_global_addr to i64), [[TMP1]]
171171
; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_inline5_align to i64))
172172
; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_inline5_size_m1 to i64)
173-
; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP11:%.*]]
173+
; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP11:%.*]], !prof [[PROF6]]
174174
; X86: 5:
175175
; X86-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP3]] to i32
176176
; X86-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 31
@@ -188,7 +188,7 @@ define i1 @inline5(ptr %p) {
188188
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_inline5_global_addr to i64), [[TMP1]]
189189
; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 5)
190190
; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 31
191-
; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP11:%.*]]
191+
; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP11:%.*]], !prof [[PROF0]]
192192
; ARM: 5:
193193
; ARM-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP3]] to i32
194194
; ARM-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 31
@@ -211,7 +211,7 @@ define i1 @inline6(ptr %p) {
211211
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_inline6_global_addr to i64), [[TMP1]]
212212
; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_inline6_align to i64))
213213
; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_inline6_size_m1 to i64)
214-
; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
214+
; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]], !prof [[PROF6]]
215215
; X86: 5:
216216
; X86-NEXT: [[TMP6:%.*]] = and i64 [[TMP3]], 63
217217
; X86-NEXT: [[TMP7:%.*]] = shl i64 1, [[TMP6]]
@@ -228,7 +228,7 @@ define i1 @inline6(ptr %p) {
228228
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_inline6_global_addr to i64), [[TMP1]]
229229
; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 6)
230230
; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 63
231-
; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
231+
; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]], !prof [[PROF0]]
232232
; ARM: 5:
233233
; ARM-NEXT: [[TMP6:%.*]] = and i64 [[TMP3]], 63
234234
; ARM-NEXT: [[TMP7:%.*]] = shl i64 1, [[TMP6]]
@@ -257,13 +257,16 @@ define i1 @single(ptr %p) {
257257
; X86: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
258258
; X86: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
259259
;.
260+
; ARM: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
261+
; ARM: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
262+
;.
260263
; X86: [[META0]] = !{i64 0, i64 256}
261264
; X86: [[META1]] = !{i64 0, i64 64}
262265
; X86: [[META2]] = !{i64 -1, i64 -1}
263266
; X86: [[META3]] = !{i64 0, i64 32}
264267
; X86: [[META4]] = !{i64 0, i64 4294967296}
265268
; X86: [[META5]] = !{i64 0, i64 128}
269+
; X86: [[PROF6]] = !{!"branch_weights", i32 1048575, i32 1}
266270
;.
267-
; ARM: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
268-
; ARM: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
271+
; ARM: [[PROF0]] = !{!"branch_weights", i32 1048575, i32 1}
269272
;.

‎llvm/utils/profcheck-xfail.txt‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -490,8 +490,6 @@ Transforms/LowerSwitch/do-not-handle-impossible-values.ll
490490
Transforms/LowerSwitch/feature.ll
491491
Transforms/LowerSwitch/fold-popular-case-to-unreachable-default.ll
492492
Transforms/LowerSwitch/pr59316.ll
493-
Transforms/LowerTypeTests/import.ll
494-
Transforms/LowerTypeTests/simple.ll
495493
Transforms/MergeFunc/2011-02-08-RemoveEqual.ll
496494
Transforms/MergeFunc/apply_function_attributes.ll
497495
Transforms/MergeFunc/call-and-invoke-with-ranges-attr.ll

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