@@ -2662,20 +2662,17 @@ bool PPCFrameLowering::restoreCalleeSavedRegisters(
26622662 if (Restored[Dst])
26632663 continue ;
26642664
2665- if (VSRContainingGPRs[Dst].second != 0 ) {
2665+ const auto &VSR = VSRContainingGPRs[Dst];
2666+ if (VSR.second != 0 ) {
26662667 assert (Subtarget.hasP9Vector ());
26672668 NumPEReloadVSR += 2 ;
2668- BuildMI (MBB, I, DL, TII.get (PPC::MFVSRLD),
2669- VSRContainingGPRs[Dst].second )
2670- .addReg (Dst);
2671- BuildMI (MBB, I, DL, TII.get (PPC::MFVSRD),
2672- VSRContainingGPRs[Dst].first )
2669+ BuildMI (MBB, I, DL, TII.get (PPC::MFVSRLD), VSR.second ).addReg (Dst);
2670+ BuildMI (MBB, I, DL, TII.get (PPC::MFVSRD), VSR.first )
26732671 .addReg (TRI->getSubReg (Dst, PPC::sub_64), getKillRegState (true ));
2674- } else if (VSRContainingGPRs[Dst] .second == 0 ) {
2672+ } else if (VSR .second == 0 ) {
26752673 assert (Subtarget.hasP8Vector ());
26762674 ++NumPEReloadVSR;
2677- BuildMI (MBB, I, DL, TII.get (PPC::MFVSRD),
2678- VSRContainingGPRs[Dst].first )
2675+ BuildMI (MBB, I, DL, TII.get (PPC::MFVSRD), VSR.first )
26792676 .addReg (TRI->getSubReg (Dst, PPC::sub_64), getKillRegState (true ));
26802677 } else {
26812678 llvm_unreachable (" More than two GPRs spilled to a VSR!" );
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