Addressed the review comments2

Author: JaydeepChauhan14

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

@@ -5456,37 +5456,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
     break;
   }
 
-  case X86ISD::FP_TO_SINT_SAT:
-  case X86ISD::FP_TO_UINT_SAT: {
-    assert(Subtarget->hasAVX10_2() && "Unsupported node");
-    bool IsSigned = Node->getOpcode() == X86ISD::FP_TO_SINT_SAT;
-    SDValue Op = Node->getOperand(0);
-    EVT VT = Node->getValueType(0);
-    EVT OpVT = Op.getValueType();
-    MachineSDNode *MachineNode;
-
-    if (VT == MVT::v4i32 && OpVT == MVT::v4f32) {
-      if (IsSigned)
-        MachineNode =
-            CurDAG->getMachineNode(X86::VCVTTPD2DQSZ128rr, dl, MVT::v4i32, Op);
-      else
-        MachineNode =
-            CurDAG->getMachineNode(X86::VCVTTPD2UDQSZ128rr, dl, MVT::v4i32, Op);
-    }
-
-    if ((VT == MVT::v2i64 && OpVT == MVT::v2f64)) {
-      if (IsSigned)
-        MachineNode =
-            CurDAG->getMachineNode(X86::VCVTTPS2QQSZ128rr, dl, MVT::v2i64, Op);
-      else
-        MachineNode =
-            CurDAG->getMachineNode(X86::VCVTTPS2UQQSZ128rr, dl, MVT::v2i64, Op);
-    }
-
-    SDValue NewNode = SDValue(MachineNode, 0);
-    ReplaceNode(Node, NewNode.getNode());
-    return;
-  }
   case X86ISD::ANDNP:
     if (tryVPTERNLOG(Node))
       return;

llvm/lib/Target/X86/X86InstrAVX10.td

@@ -835,6 +835,8 @@ let Predicates = [HasAVX10_2] in {
 // Patterns VCVTTPD2DQSZ128
 
 // VCVTTPD2DQS
+def : Pat<(v4i32(X86fp2sisat(v4f32 VR128X:$src))),
+          (VCVTTPD2DQSZ128rr VR128X:$src)>;
 def : Pat<(v4i32(fp_to_sint_sat(v4f64 VR256X:$src), i32)),
           (VCVTTPD2DQSZ256rr VR256X:$src)>;
 def : Pat<(v8i32(fp_to_sint_sat(v8f64 VR512:$src), i32)),
@@ -849,6 +851,8 @@ def : Pat<(v8i64(fp_to_sint_sat(v8f64 VR512:$src), i64)),
           (VCVTTPD2QQSZrr VR512:$src)>;
 
 // VCVTTPD2UDQS
+def : Pat<(v4i32(X86fp2uisat(v4f32 VR128X:$src))),
+          (VCVTTPD2UDQSZ128rr VR128X:$src)>;
 def : Pat<(v4i32(fp_to_uint_sat(v4f64 VR256X:$src), i32)),
           (VCVTTPD2UDQSZ256rr VR256X:$src)>;
 def : Pat<(v8i32(fp_to_uint_sat(v8f64 VR512:$src), i32)),
@@ -871,6 +875,8 @@ def : Pat<(v16i32(fp_to_sint_sat(v16f32 VR512:$src), i32)),
           (VCVTTPS2DQSZrr VR512:$src)>;
 
 // VCVTTPS2QQS
+def : Pat<(v2i64(X86fp2sisat(v2f64 VR128X:$src))),
+          (VCVTTPS2QQSZ128rr VR128X:$src)>;
 def : Pat<(v4i64(fp_to_sint_sat(v4f32 VR128X:$src), i64)),
           (VCVTTPS2QQSZ256rr VR128X:$src)>;
 def : Pat<(v8i64(fp_to_sint_sat(v8f32 VR256X:$src), i64)),
@@ -885,6 +891,8 @@ def : Pat<(v16i32(fp_to_uint_sat(v16f32 VR512:$src), i32)),
           (VCVTTPS2UDQSZrr VR512:$src)>;
 
 // VCVTTPS2UQQS
+def : Pat<(v2i64(X86fp2uisat(v2f64 VR128X:$src))),
+          (VCVTTPS2UQQSZ128rr VR128X:$src)>;
 def : Pat<(v4i64(fp_to_uint_sat(v4f32 VR128X:$src), i64)),
           (VCVTTPS2UQQSZ256rr VR128X:$src)>;
 def : Pat<(v8i64(fp_to_uint_sat(v8f32 VR256X:$src), i64)),

llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

@@ -390,6 +390,13 @@ def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>,
                            SDTCisFP<0>, SDTCisVT<4, i32>]>;
 
+def SDTFPToxIntSatOp
+    : SDTypeProfile<1,
+                    1, [SDTCisVec<0>, SDTCisVec<1>, SDTCisInt<0>, SDTCisFP<1>]>;
+
+def X86fp2sisat : SDNode<"X86ISD::FP_TO_SINT_SAT", SDTFPToxIntSatOp>;
+def X86fp2uisat : SDNode<"X86ISD::FP_TO_UINT_SAT", SDTFPToxIntSatOp>;
+
 def X86PAlignr : SDNode<"X86ISD::PALIGNR",
                         SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i8>,
                                              SDTCisSameAs<0,1>,