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[LoongArch] Support vector types for hasAndNot to enable more DAG combines (#159056)
After this commit, DAGCombiner will have more opportunities to optimize vector types `and+...+not` to `andn`. Many combines in DAGCombiner will be enabled, but only shows changes after combining `and(add(not))` to `and(not(sub))` in the tests of this commit.
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3 files changed

+22
-32
lines changed

3 files changed

+22
-32
lines changed

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8571,8 +8571,12 @@ EVT LoongArchTargetLowering::getSetCCResultType(const DataLayout &DL,
85718571
}
85728572

85738573
bool LoongArchTargetLowering::hasAndNot(SDValue Y) const {
8574-
// TODO: Support vectors.
8575-
return Y.getValueType().isScalarInteger() && !isa<ConstantSDNode>(Y);
8574+
EVT VT = Y.getValueType();
8575+
8576+
if (VT.isVector())
8577+
return Subtarget.hasExtLSX() && VT.isInteger();
8578+
8579+
return VT.isScalarInteger() && !isa<ConstantSDNode>(Y);
85768580
}
85778581

85788582
bool LoongArchTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,

‎llvm/test/CodeGen/LoongArch/lasx/and-not-combine.ll‎

Lines changed: 8 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,8 @@ define void @and_not_combine_v32i8(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind
88
; CHECK-NEXT: xvld $xr0, $a2, 0
99
; CHECK-NEXT: xvld $xr1, $a3, 0
1010
; CHECK-NEXT: xvld $xr2, $a1, 0
11-
; CHECK-NEXT: xvxori.b $xr0, $xr0, 255
12-
; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1
13-
; CHECK-NEXT: xvand.v $xr0, $xr2, $xr0
11+
; CHECK-NEXT: xvsub.b $xr0, $xr0, $xr1
12+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr2
1413
; CHECK-NEXT: xvst $xr0, $a0, 0
1514
; CHECK-NEXT: ret
1615
entry:
@@ -30,10 +29,8 @@ define void @and_not_combine_v16i16(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwin
3029
; CHECK-NEXT: xvld $xr0, $a2, 0
3130
; CHECK-NEXT: xvld $xr1, $a3, 0
3231
; CHECK-NEXT: xvld $xr2, $a1, 0
33-
; CHECK-NEXT: xvrepli.b $xr3, -1
34-
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr3
35-
; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1
36-
; CHECK-NEXT: xvand.v $xr0, $xr2, $xr0
32+
; CHECK-NEXT: xvsub.h $xr0, $xr0, $xr1
33+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr2
3734
; CHECK-NEXT: xvst $xr0, $a0, 0
3835
; CHECK-NEXT: ret
3936
entry:
@@ -53,10 +50,8 @@ define void @and_not_combine_v8i32(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind
5350
; CHECK-NEXT: xvld $xr0, $a2, 0
5451
; CHECK-NEXT: xvld $xr1, $a3, 0
5552
; CHECK-NEXT: xvld $xr2, $a1, 0
56-
; CHECK-NEXT: xvrepli.b $xr3, -1
57-
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr3
58-
; CHECK-NEXT: xvadd.w $xr0, $xr0, $xr1
59-
; CHECK-NEXT: xvand.v $xr0, $xr2, $xr0
53+
; CHECK-NEXT: xvsub.w $xr0, $xr0, $xr1
54+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr2
6055
; CHECK-NEXT: xvst $xr0, $a0, 0
6156
; CHECK-NEXT: ret
6257
entry:
@@ -76,10 +71,8 @@ define void @and_not_combine_v4i64(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind
7671
; CHECK-NEXT: xvld $xr0, $a2, 0
7772
; CHECK-NEXT: xvld $xr1, $a3, 0
7873
; CHECK-NEXT: xvld $xr2, $a1, 0
79-
; CHECK-NEXT: xvrepli.b $xr3, -1
80-
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr3
81-
; CHECK-NEXT: xvadd.d $xr0, $xr0, $xr1
82-
; CHECK-NEXT: xvand.v $xr0, $xr2, $xr0
74+
; CHECK-NEXT: xvsub.d $xr0, $xr0, $xr1
75+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr2
8376
; CHECK-NEXT: xvst $xr0, $a0, 0
8477
; CHECK-NEXT: ret
8578
entry:

‎llvm/test/CodeGen/LoongArch/lsx/and-not-combine.ll‎

Lines changed: 8 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,8 @@ define void @and_not_combine_v16i8(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind
88
; CHECK-NEXT: vld $vr0, $a2, 0
99
; CHECK-NEXT: vld $vr1, $a3, 0
1010
; CHECK-NEXT: vld $vr2, $a1, 0
11-
; CHECK-NEXT: vxori.b $vr0, $vr0, 255
12-
; CHECK-NEXT: vadd.b $vr0, $vr0, $vr1
13-
; CHECK-NEXT: vand.v $vr0, $vr2, $vr0
11+
; CHECK-NEXT: vsub.b $vr0, $vr0, $vr1
12+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr2
1413
; CHECK-NEXT: vst $vr0, $a0, 0
1514
; CHECK-NEXT: ret
1615
entry:
@@ -30,10 +29,8 @@ define void @and_not_combine_v8i16(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind
3029
; CHECK-NEXT: vld $vr0, $a2, 0
3130
; CHECK-NEXT: vld $vr1, $a3, 0
3231
; CHECK-NEXT: vld $vr2, $a1, 0
33-
; CHECK-NEXT: vrepli.b $vr3, -1
34-
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr3
35-
; CHECK-NEXT: vadd.h $vr0, $vr0, $vr1
36-
; CHECK-NEXT: vand.v $vr0, $vr2, $vr0
32+
; CHECK-NEXT: vsub.h $vr0, $vr0, $vr1
33+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr2
3734
; CHECK-NEXT: vst $vr0, $a0, 0
3835
; CHECK-NEXT: ret
3936
entry:
@@ -53,10 +50,8 @@ define void @and_not_combine_v4i32(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind
5350
; CHECK-NEXT: vld $vr0, $a2, 0
5451
; CHECK-NEXT: vld $vr1, $a3, 0
5552
; CHECK-NEXT: vld $vr2, $a1, 0
56-
; CHECK-NEXT: vrepli.b $vr3, -1
57-
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr3
58-
; CHECK-NEXT: vadd.w $vr0, $vr0, $vr1
59-
; CHECK-NEXT: vand.v $vr0, $vr2, $vr0
53+
; CHECK-NEXT: vsub.w $vr0, $vr0, $vr1
54+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr2
6055
; CHECK-NEXT: vst $vr0, $a0, 0
6156
; CHECK-NEXT: ret
6257
entry:
@@ -76,10 +71,8 @@ define void @and_not_combine_v2i64(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind
7671
; CHECK-NEXT: vld $vr0, $a2, 0
7772
; CHECK-NEXT: vld $vr1, $a3, 0
7873
; CHECK-NEXT: vld $vr2, $a1, 0
79-
; CHECK-NEXT: vrepli.b $vr3, -1
80-
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr3
81-
; CHECK-NEXT: vadd.d $vr0, $vr0, $vr1
82-
; CHECK-NEXT: vand.v $vr0, $vr2, $vr0
74+
; CHECK-NEXT: vsub.d $vr0, $vr0, $vr1
75+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr2
8376
; CHECK-NEXT: vst $vr0, $a0, 0
8477
; CHECK-NEXT: ret
8578
entry:

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