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[TableGen][DecoderEmitter] Add option to emit type-specialized decodeToMCInst 
1 parent b20bbd4 commit 94522ba

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21 files changed

+552
-263
lines changed

21 files changed

+552
-263
lines changed

‎llvm/include/llvm/Target/Target.td‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1137,7 +1137,6 @@ class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
11371137
let MIOperandInfo = OpTypes;
11381138
}
11391139

1140-
11411140
// InstrInfo - This class should only be instantiated once to provide parameters
11421141
// which are global to the target machine.
11431142
//
@@ -1158,6 +1157,12 @@ class InstrInfo {
11581157
//
11591158
// This option is a temporary migration help. It will go away.
11601159
bit guessInstructionProperties = true;
1160+
1161+
// Option to choose bewteen templated and non-templated code from decoder
1162+
// emitter. This means that the generated `decodeInstruction` function will
1163+
// use auto-inferred types for the instruction payload instead of generating
1164+
// templated code using `InsnType` for the instruction payload.
1165+
bit GenerateTemplatedDecoder = false;
11611166
}
11621167

11631168
// Standard Pseudo Instructions.

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp‎

Lines changed: 15 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@
3535
#include "llvm/MC/TargetRegistry.h"
3636
#include "llvm/Support/AMDHSAKernelDescriptor.h"
3737
#include "llvm/Support/Compiler.h"
38+
#include <bitset>
3839

3940
using namespace llvm;
4041

@@ -497,26 +498,24 @@ template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
497498
return Res;
498499
}
499500

500-
static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) {
501+
static inline std::bitset<96> eat12Bytes(ArrayRef<uint8_t> &Bytes) {
502+
using namespace llvm::support::endian;
501503
assert(Bytes.size() >= 12);
502-
uint64_t Lo =
503-
support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data());
504+
std::bitset<96> Lo(read<uint64_t, endianness::little>(Bytes.data()));
504505
Bytes = Bytes.slice(8);
505-
uint64_t Hi =
506-
support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data());
506+
std::bitset<96> Hi(read<uint32_t, endianness::little>(Bytes.data()));
507507
Bytes = Bytes.slice(4);
508-
return DecoderUInt128(Lo, Hi);
508+
return (Hi << 64) | Lo;
509509
}
510510

511-
static inline DecoderUInt128 eat16Bytes(ArrayRef<uint8_t> &Bytes) {
511+
static inline std::bitset<128> eat16Bytes(ArrayRef<uint8_t> &Bytes) {
512+
using namespace llvm::support::endian;
512513
assert(Bytes.size() >= 16);
513-
uint64_t Lo =
514-
support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data());
514+
std::bitset<128> Lo(read<uint64_t, endianness::little>(Bytes.data()));
515515
Bytes = Bytes.slice(8);
516-
uint64_t Hi =
517-
support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data());
516+
std::bitset<128> Hi(read<uint64_t, endianness::little>(Bytes.data()));
518517
Bytes = Bytes.slice(8);
519-
return DecoderUInt128(Lo, Hi);
518+
return (Hi << 64) | Lo;
520519
}
521520

522521
void AMDGPUDisassembler::decodeImmOperands(MCInst &MI,
@@ -599,14 +598,14 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
599598
// Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
600599
// encodings
601600
if (isGFX1250() && Bytes.size() >= 16) {
602-
DecoderUInt128 DecW = eat16Bytes(Bytes);
601+
std::bitset<128> DecW = eat16Bytes(Bytes);
603602
if (tryDecodeInst(DecoderTableGFX1250128, MI, DecW, Address, CS))
604603
break;
605604
Bytes = Bytes_.slice(0, MaxInstBytesNum);
606605
}
607606

608-
if (isGFX11Plus() && Bytes.size() >= 12 ) {
609-
DecoderUInt128 DecW = eat12Bytes(Bytes);
607+
if (isGFX11Plus() && Bytes.size() >= 12) {
608+
std::bitset<96> DecW = eat12Bytes(Bytes);
610609

611610
if (isGFX11() &&
612611
tryDecodeInst(DecoderTableGFX1196, DecoderTableGFX11_FAKE1696, MI,
@@ -641,7 +640,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
641640

642641
} else if (Bytes.size() >= 16 &&
643642
STI.hasFeature(AMDGPU::FeatureGFX950Insts)) {
644-
DecoderUInt128 DecW = eat16Bytes(Bytes);
643+
std::bitset<128> DecW = eat16Bytes(Bytes);
645644
if (tryDecodeInst(DecoderTableGFX940128, MI, DecW, Address, CS))
646645
break;
647646

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h‎

Lines changed: 0 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -32,44 +32,6 @@ class MCOperand;
3232
class MCSubtargetInfo;
3333
class Twine;
3434

35-
// Exposes an interface expected by autogenerated code in
36-
// FixedLenDecoderEmitter
37-
class DecoderUInt128 {
38-
private:
39-
uint64_t Lo = 0;
40-
uint64_t Hi = 0;
41-
42-
public:
43-
DecoderUInt128() = default;
44-
DecoderUInt128(uint64_t Lo, uint64_t Hi = 0) : Lo(Lo), Hi(Hi) {}
45-
operator bool() const { return Lo || Hi; }
46-
uint64_t extractBitsAsZExtValue(unsigned NumBits,
47-
unsigned BitPosition) const {
48-
assert(NumBits && NumBits <= 64);
49-
assert(BitPosition < 128);
50-
uint64_t Val;
51-
if (BitPosition < 64)
52-
Val = Lo >> BitPosition | Hi << 1 << (63 - BitPosition);
53-
else
54-
Val = Hi >> (BitPosition - 64);
55-
return Val & ((uint64_t(2) << (NumBits - 1)) - 1);
56-
}
57-
DecoderUInt128 operator&(const DecoderUInt128 &RHS) const {
58-
return DecoderUInt128(Lo & RHS.Lo, Hi & RHS.Hi);
59-
}
60-
DecoderUInt128 operator&(const uint64_t &RHS) const {
61-
return *this & DecoderUInt128(RHS);
62-
}
63-
DecoderUInt128 operator~() const { return DecoderUInt128(~Lo, ~Hi); }
64-
bool operator==(const DecoderUInt128 &RHS) {
65-
return Lo == RHS.Lo && Hi == RHS.Hi;
66-
}
67-
bool operator!=(const DecoderUInt128 &RHS) {
68-
return Lo != RHS.Lo || Hi != RHS.Hi;
69-
}
70-
bool operator!=(const int &RHS) { return *this != DecoderUInt128(RHS); }
71-
};
72-
7335
//===----------------------------------------------------------------------===//
7436
// AMDGPUDisassembler
7537
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/ARC/ARC.td‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,10 @@ include "ARCRegisterInfo.td"
2424
include "ARCInstrInfo.td"
2525
include "ARCCallingConv.td"
2626

27-
def ARCInstrInfo : InstrInfo;
27+
def ARCInstrInfo : InstrInfo {
28+
// FIXME: Migrate ARC disassembler to work with non-templated decoder.
29+
let GenerateTemplatedDecoder = true;
30+
}
2831

2932
class Proc<string Name, list<SubtargetFeature> Features>
3033
: Processor<Name, NoItineraries, Features>;

‎llvm/lib/Target/AVR/AVR.td‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,10 @@ include "AVRRegisterInfo.td"
3232

3333
include "AVRInstrInfo.td"
3434

35-
def AVRInstrInfo : InstrInfo;
35+
def AVRInstrInfo : InstrInfo {
36+
// FIXME: Migrate AVR disassembler to work with non-templated decoder.
37+
let GenerateTemplatedDecoder = true;
38+
}
3639

3740
//===---------------------------------------------------------------------===//
3841
// Calling Conventions

‎llvm/lib/Target/CSKY/CSKY.td‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -671,7 +671,10 @@ def : CK860V<"ck860fv", NoSchedModel,
671671
// Define the CSKY target.
672672
//===----------------------------------------------------------------------===//
673673

674-
def CSKYInstrInfo : InstrInfo;
674+
def CSKYInstrInfo : InstrInfo {
675+
// FIXME: Migrate CSKY disassembler to work with non-templated decoder.
676+
let GenerateTemplatedDecoder = true;
677+
}
675678

676679

677680
def CSKYAsmParser : AsmParser {

‎llvm/lib/Target/MSP430/MSP430.td‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,10 @@ include "MSP430CallingConv.td"
6161

6262
include "MSP430InstrInfo.td"
6363

64-
def MSP430InstrInfo : InstrInfo;
64+
def MSP430InstrInfo : InstrInfo {
65+
// FIXME: Migrate MPS430 disassembler to work with non-templated decoder.
66+
let GenerateTemplatedDecoder = true;
67+
}
6568

6669
//===---------------------------------------------------------------------===//
6770
// Assembly Printers

‎llvm/lib/Target/Mips/Mips.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -229,6 +229,8 @@ include "MipsScheduleP5600.td"
229229
include "MipsScheduleGeneric.td"
230230

231231
def MipsInstrInfo : InstrInfo {
232+
// FIXME: Migrate MIPS disassembler to work with non-templated decoder.
233+
let GenerateTemplatedDecoder = true;
232234
}
233235

234236
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/PowerPC/PPC.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -721,6 +721,8 @@ include "PPCCallingConv.td"
721721

722722
def PPCInstrInfo : InstrInfo {
723723
let isLittleEndianEncoding = 1;
724+
// FIXME: Migrate PPC disassembler to work with non-templated decoder.
725+
let GenerateTemplatedDecoder = true;
724726
}
725727

726728
def PPCAsmWriter : AsmWriter {

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -712,9 +712,7 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
712712
}
713713
Size = 4;
714714

715-
// Use uint64_t to match getInstruction48. decodeInstruction is templated
716-
// on the Insn type.
717-
uint64_t Insn = support::endian::read32le(Bytes.data());
715+
uint32_t Insn = support::endian::read32le(Bytes.data());
718716

719717
for (const DecoderListEntry &Entry : DecoderList32) {
720718
if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
@@ -760,9 +758,7 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
760758
}
761759
Size = 2;
762760

763-
// Use uint64_t to match getInstruction48. decodeInstruction is templated
764-
// on the Insn type.
765-
uint64_t Insn = support::endian::read16le(Bytes.data());
761+
uint16_t Insn = support::endian::read16le(Bytes.data());
766762

767763
for (const DecoderListEntry &Entry : DecoderList16) {
768764
if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
@@ -796,9 +792,10 @@ DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
796792
}
797793
Size = 6;
798794

799-
uint64_t Insn = 0;
795+
uint64_t InsnBits = 0;
800796
for (size_t i = Size; i-- != 0;)
801-
Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i);
797+
InsnBits += (static_cast<uint64_t>(Bytes[i]) << 8 * i);
798+
std::bitset<48> Insn(InsnBits);
802799

803800
for (const DecoderListEntry &Entry : DecoderList48) {
804801
if (!Entry.haveContainedFeatures(STI.getFeatureBits()))

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