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[RISCV] Add policy operand to masked vector compare pseudos. Remove ForceTailAgnostic. NFC (#127575)
Add a policy operand to set the tail agnostic policy instead of using ForceTailAgnostic. The masked to unmasked transforms had to be updated to drop the policy operand when converting to unmasked.
1 parent 378c6fb commit 9516f44

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8 files changed

+64
-62
lines changed

8 files changed

+64
-62
lines changed

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -65,13 +65,9 @@ enum {
6565
VLMulShift = ConstraintShift + 3,
6666
VLMulMask = 0b111 << VLMulShift,
6767

68-
// Force a tail agnostic policy even this instruction has a tied destination.
69-
ForceTailAgnosticShift = VLMulShift + 3,
70-
ForceTailAgnosticMask = 1 << ForceTailAgnosticShift,
71-
7268
// Is this a _TIED vector pseudo instruction. For these instructions we
7369
// shouldn't skip the tied operand when converting to MC instructions.
74-
IsTiedPseudoShift = ForceTailAgnosticShift + 1,
70+
IsTiedPseudoShift = VLMulShift + 3,
7571
IsTiedPseudoMask = 1 << IsTiedPseudoShift,
7672

7773
// Does this instruction have a SEW operand. It will be the last explicit
@@ -148,10 +144,6 @@ static inline unsigned getFormat(uint64_t TSFlags) {
148144
static inline VLMUL getLMul(uint64_t TSFlags) {
149145
return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
150146
}
151-
/// \returns true if tail agnostic is enforced for the instruction.
152-
static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
153-
return TSFlags & ForceTailAgnosticMask;
154-
}
155147
/// \returns true if this a _TIED pseudo.
156148
static inline bool isTiedPseudo(uint64_t TSFlags) {
157149
return TSFlags & IsTiedPseudoMask;

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 18 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1838,13 +1838,16 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
18381838
return;
18391839
}
18401840

1841+
SDValue PolicyOp =
1842+
CurDAG->getTargetConstant(RISCVII::TAIL_AGNOSTIC, DL, XLenVT);
1843+
18411844
if (IsCmpConstant) {
18421845
SDValue Imm =
18431846
selectImm(CurDAG, SDLoc(Src2), XLenVT, CVal - 1, *Subtarget);
18441847

18451848
ReplaceNode(Node, CurDAG->getMachineNode(
18461849
VMSGTMaskOpcode, DL, VT,
1847-
{MaskedOff, Src1, Imm, Mask, VL, SEW}));
1850+
{MaskedOff, Src1, Imm, Mask, VL, SEW, PolicyOp}));
18481851
return;
18491852
}
18501853

@@ -1853,10 +1856,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
18531856
// The result is mask undisturbed.
18541857
// We use the same instructions to emulate mask agnostic behavior, because
18551858
// the agnostic result can be either undisturbed or all 1.
1856-
SDValue Cmp = SDValue(
1857-
CurDAG->getMachineNode(VMSLTMaskOpcode, DL, VT,
1858-
{MaskedOff, Src1, Src2, Mask, VL, SEW}),
1859-
0);
1859+
SDValue Cmp = SDValue(CurDAG->getMachineNode(VMSLTMaskOpcode, DL, VT,
1860+
{MaskedOff, Src1, Src2, Mask,
1861+
VL, SEW, PolicyOp}),
1862+
0);
18601863
// vmxor.mm vd, vd, v0 is used to update active value.
18611864
ReplaceNode(Node, CurDAG->getMachineNode(VMXOROpcode, DL, VT,
18621865
{Cmp, Mask, VL, MaskSEW}));
@@ -3792,9 +3795,9 @@ bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(MachineSDNode *N) {
37923795
const MCInstrDesc &MaskedMCID = TII->get(N->getMachineOpcode());
37933796
const bool MaskedHasPassthru = RISCVII::isFirstDefTiedToFirstUse(MaskedMCID);
37943797

3795-
assert(RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags) ==
3796-
RISCVII::hasVecPolicyOp(MCID.TSFlags) &&
3797-
"Masked and unmasked pseudos are inconsistent");
3798+
assert((RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags) ||
3799+
!RISCVII::hasVecPolicyOp(MCID.TSFlags)) &&
3800+
"Unmasked pseudo has policy but masked pseudo doesn't?");
37983801
assert(RISCVII::hasVecPolicyOp(MCID.TSFlags) == HasPassthru &&
37993802
"Unexpected pseudo structure");
38003803
assert(!(HasPassthru && !MaskedHasPassthru) &&
@@ -3803,11 +3806,18 @@ bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(MachineSDNode *N) {
38033806
SmallVector<SDValue, 8> Ops;
38043807
// Skip the passthru operand at index 0 if the unmasked don't have one.
38053808
bool ShouldSkip = !HasPassthru && MaskedHasPassthru;
3809+
bool DropPolicy = !RISCVII::hasVecPolicyOp(MCID.TSFlags) &&
3810+
RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags);
3811+
bool HasChainOp =
3812+
N->getOperand(N->getNumOperands() - 1).getValueType() == MVT::Other;
3813+
unsigned LastOpNum = N->getNumOperands() - 1 - HasChainOp;
38063814
for (unsigned I = ShouldSkip, E = N->getNumOperands(); I != E; I++) {
38073815
// Skip the mask
38083816
SDValue Op = N->getOperand(I);
38093817
if (I == MaskOpIdx)
38103818
continue;
3819+
if (DropPolicy && I == LastOpNum)
3820+
continue;
38113821
Ops.push_back(Op);
38123822
}
38133823

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1049,11 +1049,6 @@ RISCVInsertVSETVLI::computeInfoForInstr(const MachineInstr &MI) const {
10491049
MaskAgnostic = Policy & RISCVII::MASK_AGNOSTIC;
10501050
}
10511051

1052-
// Some pseudo instructions force a tail agnostic policy despite having a
1053-
// tied def.
1054-
if (RISCVII::doesForceTailAgnostic(TSFlags))
1055-
TailAgnostic = true;
1056-
10571052
if (!RISCVII::usesMaskPolicy(TSFlags))
10581053
MaskAgnostic = true;
10591054
}

‎llvm/lib/Target/RISCV/RISCVInstrFormats.td‎

Lines changed: 13 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -193,44 +193,41 @@ class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,
193193
bits<3> VLMul = 0;
194194
let TSFlags{10-8} = VLMul;
195195

196-
bit ForceTailAgnostic = false;
197-
let TSFlags{11} = ForceTailAgnostic;
198-
199196
bit IsTiedPseudo = 0;
200-
let TSFlags{12} = IsTiedPseudo;
197+
let TSFlags{11} = IsTiedPseudo;
201198

202199
bit HasSEWOp = 0;
203-
let TSFlags{13} = HasSEWOp;
200+
let TSFlags{12} = HasSEWOp;
204201

205202
bit HasVLOp = 0;
206-
let TSFlags{14} = HasVLOp;
203+
let TSFlags{13} = HasVLOp;
207204

208205
bit HasVecPolicyOp = 0;
209-
let TSFlags{15} = HasVecPolicyOp;
206+
let TSFlags{14} = HasVecPolicyOp;
210207

211208
bit IsRVVWideningReduction = 0;
212-
let TSFlags{16} = IsRVVWideningReduction;
209+
let TSFlags{15} = IsRVVWideningReduction;
213210

214211
bit UsesMaskPolicy = 0;
215-
let TSFlags{17} = UsesMaskPolicy;
212+
let TSFlags{16} = UsesMaskPolicy;
216213

217214
// Indicates that the result can be considered sign extended from bit 31. Some
218215
// instructions with this flag aren't W instructions, but are either sign
219216
// extended from a smaller size, always outputs a small integer, or put zeros
220217
// in bits 63:31. Used by the SExtWRemoval pass.
221218
bit IsSignExtendingOpW = 0;
222-
let TSFlags{18} = IsSignExtendingOpW;
219+
let TSFlags{17} = IsSignExtendingOpW;
223220

224221
bit HasRoundModeOp = 0;
225-
let TSFlags{19} = HasRoundModeOp;
222+
let TSFlags{18} = HasRoundModeOp;
226223

227224
// This is only valid when HasRoundModeOp is set to 1. HasRoundModeOp is set
228225
// to 1 for vector fixed-point or floating-point intrinsics. This bit is
229226
// processed under pass 'RISCVInsertReadWriteCSR' pass to distinguish between
230227
// fixed-point / floating-point instructions and emit appropriate read/write
231228
// to the correct CSR.
232229
bit UsesVXRM = 0;
233-
let TSFlags{20} = UsesVXRM;
230+
let TSFlags{19} = UsesVXRM;
234231

235232
// Indicates whether these instructions can partially overlap between source
236233
// registers and destination registers according to the vector spec.
@@ -239,19 +236,19 @@ class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,
239236
// 2 -> narrowing case
240237
// 3 -> widening case
241238
bits<2> TargetOverlapConstraintType = 0;
242-
let TSFlags{22-21} = TargetOverlapConstraintType;
239+
let TSFlags{21-20} = TargetOverlapConstraintType;
243240

244241
// Most vector instructions are elementwise, but some may depend on the value
245242
// of VL (e.g. vslide1down.vx), and others may depend on the VL and mask
246243
// (e.g. vredsum.vs, viota.m). Mark these instructions so that peepholes avoid
247244
// changing their VL and/or mask.
248245
EltDeps ElementsDependOn = EltDepsNone;
249-
let TSFlags{23} = ElementsDependOn.VL;
250-
let TSFlags{24} = ElementsDependOn.Mask;
246+
let TSFlags{22} = ElementsDependOn.VL;
247+
let TSFlags{23} = ElementsDependOn.Mask;
251248

252249
// Indicates the EEW of a vector instruction's destination operand.
253250
EEW DestEEW = EEWSEWx1;
254-
let TSFlags{26-25} = DestEEW.Value;
251+
let TSFlags{25-24} = DestEEW.Value;
255252
}
256253

257254
class RVInst<dag outs, dag ins, string opcodestr, string argstr,

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1409,7 +1409,7 @@ class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
14091409
let hasPostISelHook = 1;
14101410
}
14111411

1412-
// Like VPseudoBinaryMaskPolicy, but output can be V0 and there is no policy.
1412+
// Like VPseudoBinaryMaskPolicy, but output can be V0.
14131413
class VPseudoBinaryMOutMask<VReg RetClass,
14141414
RegisterClass Op1Class,
14151415
DAGOperand Op2Class,
@@ -1418,7 +1418,7 @@ class VPseudoBinaryMOutMask<VReg RetClass,
14181418
Pseudo<(outs RetClass:$rd),
14191419
(ins RetClass:$passthru,
14201420
Op1Class:$rs2, Op2Class:$rs1,
1421-
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
1421+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
14221422
RISCVVPseudo {
14231423
let mayLoad = 0;
14241424
let mayStore = 0;
@@ -1427,6 +1427,7 @@ class VPseudoBinaryMOutMask<VReg RetClass,
14271427
let TargetOverlapConstraintType = TargetConstraintType;
14281428
let HasVLOp = 1;
14291429
let HasSEWOp = 1;
1430+
let HasVecPolicyOp = 1;
14301431
let UsesMaskPolicy = 1;
14311432
}
14321433

@@ -2622,7 +2623,6 @@ multiclass VPseudoBinaryM<DAGOperand Op2Class, LMULInfo m, bit Commutable = 0> {
26222623
VPseudoBinaryNoMask<VR, m.vrclass, Op2Class,
26232624
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""),
26242625
TargetConstraintType = 2>;
2625-
let ForceTailAgnostic = true in
26262626
def "_" # m.MX # "_MASK" :
26272627
VPseudoBinaryMOutMask<VR, m.vrclass, Op2Class,
26282628
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""),
@@ -4140,7 +4140,7 @@ class VPatBinaryMask<string intrinsic_name,
41404140
(result_type result_reg_class:$passthru),
41414141
(op1_type op1_reg_class:$rs1),
41424142
(op2_type op2_kind:$rs2),
4143-
(mask_type VMV0:$vm), GPR:$vl, sew)>;
4143+
(mask_type VMV0:$vm), GPR:$vl, sew, TA_MU)>;
41444144

41454145
class VPatBinaryMaskPolicy<string intrinsic_name,
41464146
string inst,
@@ -4210,7 +4210,7 @@ class VPatBinaryMaskSwapped<string intrinsic_name,
42104210
(result_type result_reg_class:$passthru),
42114211
(op1_type op1_reg_class:$rs1),
42124212
(op2_type op2_kind:$rs2),
4213-
(mask_type VMV0:$vm), GPR:$vl, sew)>;
4213+
(mask_type VMV0:$vm), GPR:$vl, sew, TA_MU)>;
42144214

42154215
class VPatTiedBinaryNoMask<string intrinsic_name,
42164216
string inst,
@@ -6013,7 +6013,7 @@ multiclass VPatCompare_VI<string intrinsic, string inst,
60136013
(vti.Mask VMV0:$vm),
60146014
VLOpFrag)),
60156015
(PseudoMask VR:$passthru, vti.RegClass:$rs1, (DecImm ImmType:$rs2),
6016-
(vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW)>;
6016+
(vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MU)>;
60176017
}
60186018
}
60196019

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td‎

Lines changed: 12 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1020,7 +1020,7 @@ multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name,
10201020
VR:$passthru,
10211021
vti.RegClass:$rs1,
10221022
vti.RegClass:$rs2,
1023-
(vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW)>;
1023+
(vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MU)>;
10241024
}
10251025

10261026
// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped.
@@ -1034,7 +1034,8 @@ multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_nam
10341034
VLOpFrag)),
10351035
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK")
10361036
VR:$passthru, vti.RegClass:$rs1,
1037-
vti.RegClass:$rs2, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW)>;
1037+
vti.RegClass:$rs2, (vti.Mask VMV0:$vm), GPR:$vl,
1038+
vti.Log2SEW, TA_MU)>;
10381039
}
10391040

10401041
multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name,
@@ -1046,14 +1047,16 @@ multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_nam
10461047
(vti.Mask VMV0:$vm),
10471048
VLOpFrag)),
10481049
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
1049-
GPR:$rs2, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW)>;
1050+
GPR:$rs2, (vti.Mask VMV0:$vm), GPR:$vl,
1051+
vti.Log2SEW, TA_MU)>;
10501052
def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)),
10511053
(vti.Vector vti.RegClass:$rs1), invcc,
10521054
VR:$passthru,
10531055
(vti.Mask VMV0:$vm),
10541056
VLOpFrag)),
10551057
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
1056-
GPR:$rs2, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW)>;
1058+
GPR:$rs2, (vti.Mask VMV0:$vm), GPR:$vl,
1059+
vti.Log2SEW, TA_MU)>;
10571060
}
10581061

10591062
multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name,
@@ -1067,7 +1070,7 @@ multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_nam
10671070
VLOpFrag)),
10681071
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
10691072
XLenVT:$rs2, (vti.Mask VMV0:$vm), GPR:$vl,
1070-
vti.Log2SEW)>;
1073+
vti.Log2SEW, TA_MU)>;
10711074

10721075
// FIXME: Can do some canonicalization to remove these patterns.
10731076
def : Pat<(vti.Mask (riscv_setcc_vl (splatpat_kind simm5:$rs2),
@@ -1077,7 +1080,7 @@ multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_nam
10771080
VLOpFrag)),
10781081
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
10791082
simm5:$rs2, (vti.Mask VMV0:$vm), GPR:$vl,
1080-
vti.Log2SEW)>;
1083+
vti.Log2SEW, TA_MU)>;
10811084
}
10821085

10831086
multiclass VPatFPSetCCVL_VV_VF_FV<SDPatternOperator vop, CondCode cc,
@@ -1094,7 +1097,7 @@ multiclass VPatFPSetCCVL_VV_VF_FV<SDPatternOperator vop, CondCode cc,
10941097
(!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX#"_MASK")
10951098
VR:$passthru, fvti.RegClass:$rs1,
10961099
fvti.RegClass:$rs2, (fvti.Mask VMV0:$vm),
1097-
GPR:$vl, fvti.Log2SEW)>;
1100+
GPR:$vl, fvti.Log2SEW, TA_MU)>;
10981101
def : Pat<(fvti.Mask (vop (fvti.Vector fvti.RegClass:$rs1),
10991102
(SplatFPOp fvti.ScalarRegClass:$rs2),
11001103
cc,
@@ -1104,7 +1107,7 @@ multiclass VPatFPSetCCVL_VV_VF_FV<SDPatternOperator vop, CondCode cc,
11041107
(!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK")
11051108
VR:$passthru, fvti.RegClass:$rs1,
11061109
fvti.ScalarRegClass:$rs2, (fvti.Mask VMV0:$vm),
1107-
GPR:$vl, fvti.Log2SEW)>;
1110+
GPR:$vl, fvti.Log2SEW, TA_MU)>;
11081111
def : Pat<(fvti.Mask (vop (SplatFPOp fvti.ScalarRegClass:$rs2),
11091112
(fvti.Vector fvti.RegClass:$rs1),
11101113
cc,
@@ -1114,7 +1117,7 @@ multiclass VPatFPSetCCVL_VV_VF_FV<SDPatternOperator vop, CondCode cc,
11141117
(!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK")
11151118
VR:$passthru, fvti.RegClass:$rs1,
11161119
fvti.ScalarRegClass:$rs2, (fvti.Mask VMV0:$vm),
1117-
GPR:$vl, fvti.Log2SEW)>;
1120+
GPR:$vl, fvti.Log2SEW, TA_MU)>;
11181121
}
11191122
}
11201123
}

‎llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -466,16 +466,21 @@ bool RISCVVectorPeephole::convertToUnmasked(MachineInstr &MI) const {
466466
RISCVII::hasVecPolicyOp(MCID.TSFlags);
467467
const bool HasPassthru = RISCVII::isFirstDefTiedToFirstUse(MCID);
468468
const MCInstrDesc &MaskedMCID = TII->get(MI.getOpcode());
469-
assert(RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags) ==
470-
RISCVII::hasVecPolicyOp(MCID.TSFlags) &&
471-
"Masked and unmasked pseudos are inconsistent");
469+
assert((RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags) ||
470+
!RISCVII::hasVecPolicyOp(MCID.TSFlags)) &&
471+
"Unmasked pseudo has policy but masked pseudo doesn't?");
472472
assert(HasPolicyOp == HasPassthru && "Unexpected pseudo structure");
473473
assert(!(HasPassthru && !RISCVII::isFirstDefTiedToFirstUse(MaskedMCID)) &&
474474
"Unmasked with passthru but masked with no passthru?");
475475
(void)HasPolicyOp;
476476

477477
MI.setDesc(MCID);
478478

479+
// Drop the policy operand if unmasked doesn't need it.
480+
if (RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags) &&
481+
!RISCVII::hasVecPolicyOp(MCID.TSFlags))
482+
MI.removeOperand(RISCVII::getVecPolicyOpNum(MaskedMCID));
483+
479484
// TODO: Increment all MaskOpIdxs in tablegen by num of explicit defs?
480485
unsigned MaskOpIdx = I->MaskOpIdx + MI.getNumExplicitDefs();
481486
MI.removeOperand(MaskOpIdx);

‎llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1116,10 +1116,10 @@ body: |
11161116
bb.0:
11171117
; CHECK-LABEL: name: vmop_vv_passthru_use
11181118
; CHECK: %x:vrnov0 = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */
1119-
; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */
1119+
; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1
11201120
; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e8 */
11211121
%x:vrnov0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e1 */
1122-
%y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */
1122+
%y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1
11231123
%z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e1 */
11241124
...
11251125
---
@@ -1128,10 +1128,10 @@ body: |
11281128
bb.0:
11291129
; CHECK-LABEL: name: vmop_vv_passthru_use_incompatible_eew
11301130
; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
1131-
; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */
1131+
; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1
11321132
; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e8 */
11331133
%x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
1134-
%y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */
1134+
%y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1
11351135
%z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e1 */
11361136
...
11371137
---
@@ -1140,10 +1140,10 @@ body: |
11401140
bb.0:
11411141
; CHECK-LABEL: name: vmop_vv_passthru_use_incompatible_emul
11421142
; CHECK: %x:vrnov0 = PseudoVMAND_MM_B16 $noreg, $noreg, -1, 0 /* e8 */
1143-
; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */
1143+
; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1
11441144
; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e8 */
11451145
%x:vrnov0 = PseudoVMAND_MM_B16 $noreg, $noreg, -1, 0 /* e1 */
1146-
%y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */
1146+
%y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1
11471147
%z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e1 */
11481148
...
11491149
---

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