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davemgreendavemgreen
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[AArch64] Ensure we transferImpOps on BSP pseudo expansions. (#149456)
This ensures that we transfer implicit operands to the new expanded pseudos if necessary, similarly to other pseudo expansions.
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-30
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2 files changed

+134
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‎llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

Lines changed: 36 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -1205,32 +1205,36 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
12051205
Register DstReg = MI.getOperand(0).getReg();
12061206
if (DstReg == MI.getOperand(3).getReg()) {
12071207
// Expand to BIT
1208-
BuildMI(MBB, MBBI, MI.getDebugLoc(),
1209-
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BITv8i8
1210-
: AArch64::BITv16i8))
1211-
.add(MI.getOperand(0))
1212-
.add(MI.getOperand(3))
1213-
.add(MI.getOperand(2))
1214-
.add(MI.getOperand(1));
1208+
auto I = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1209+
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BITv8i8
1210+
: AArch64::BITv16i8))
1211+
.add(MI.getOperand(0))
1212+
.add(MI.getOperand(3))
1213+
.add(MI.getOperand(2))
1214+
.add(MI.getOperand(1));
1215+
transferImpOps(MI, I, I);
12151216
} else if (DstReg == MI.getOperand(2).getReg()) {
12161217
// Expand to BIF
1217-
BuildMI(MBB, MBBI, MI.getDebugLoc(),
1218-
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BIFv8i8
1219-
: AArch64::BIFv16i8))
1220-
.add(MI.getOperand(0))
1221-
.add(MI.getOperand(2))
1222-
.add(MI.getOperand(3))
1223-
.add(MI.getOperand(1));
1218+
auto I = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1219+
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BIFv8i8
1220+
: AArch64::BIFv16i8))
1221+
.add(MI.getOperand(0))
1222+
.add(MI.getOperand(2))
1223+
.add(MI.getOperand(3))
1224+
.add(MI.getOperand(1));
1225+
transferImpOps(MI, I, I);
12241226
} else {
12251227
// Expand to BSL, use additional move if required
12261228
if (DstReg == MI.getOperand(1).getReg()) {
1227-
BuildMI(MBB, MBBI, MI.getDebugLoc(),
1228-
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8
1229-
: AArch64::BSLv16i8))
1230-
.add(MI.getOperand(0))
1231-
.add(MI.getOperand(1))
1232-
.add(MI.getOperand(2))
1233-
.add(MI.getOperand(3));
1229+
auto I =
1230+
BuildMI(MBB, MBBI, MI.getDebugLoc(),
1231+
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8
1232+
: AArch64::BSLv16i8))
1233+
.add(MI.getOperand(0))
1234+
.add(MI.getOperand(1))
1235+
.add(MI.getOperand(2))
1236+
.add(MI.getOperand(3));
1237+
transferImpOps(MI, I, I);
12341238
} else {
12351239
BuildMI(MBB, MBBI, MI.getDebugLoc(),
12361240
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::ORRv8i8
@@ -1240,15 +1244,17 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
12401244
getRenamableRegState(MI.getOperand(0).isRenamable()))
12411245
.add(MI.getOperand(1))
12421246
.add(MI.getOperand(1));
1243-
BuildMI(MBB, MBBI, MI.getDebugLoc(),
1244-
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8
1245-
: AArch64::BSLv16i8))
1246-
.add(MI.getOperand(0))
1247-
.addReg(DstReg,
1248-
RegState::Kill |
1249-
getRenamableRegState(MI.getOperand(0).isRenamable()))
1250-
.add(MI.getOperand(2))
1251-
.add(MI.getOperand(3));
1247+
auto I2 =
1248+
BuildMI(MBB, MBBI, MI.getDebugLoc(),
1249+
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8
1250+
: AArch64::BSLv16i8))
1251+
.add(MI.getOperand(0))
1252+
.addReg(DstReg,
1253+
RegState::Kill | getRenamableRegState(
1254+
MI.getOperand(0).isRenamable()))
1255+
.add(MI.getOperand(2))
1256+
.add(MI.getOperand(3));
1257+
transferImpOps(MI, I2, I2);
12521258
}
12531259
}
12541260
MI.eraseFromParent();

‎llvm/test/CodeGen/AArch64/bsp_implicit_ops.mir

Lines changed: 98 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,98 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s
3+
4+
5+
---
6+
name: BSL_COPY
7+
tracksRegLiveness: true
8+
body: |
9+
bb.0.entry:
10+
liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
11+
12+
13+
; CHECK-LABEL: name: BSL_COPY
14+
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
15+
; CHECK-NEXT: {{ $}}
16+
; CHECK-NEXT: renamable $q2 = ORRv16i8 killed renamable $q20, killed renamable $q20
17+
; CHECK-NEXT: renamable $q2 = BSLv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
18+
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
19+
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
20+
; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
21+
; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
22+
; CHECK-NEXT: RET undef $lr, implicit $q22
23+
renamable $q2 = BSPv16i8 killed renamable $q20, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
24+
$q22 = ORRv16i8 $q0, killed $q0
25+
$q23 = ORRv16i8 $q1, killed $q1
26+
$q24 = ORRv16i8 $q2, killed $q2
27+
$q25 = ORRv16i8 $q3, killed $q3
28+
RET_ReallyLR implicit $q22
29+
...
30+
---
31+
name: BSL
32+
tracksRegLiveness: true
33+
body: |
34+
bb.0.entry:
35+
liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
36+
37+
; CHECK-LABEL: name: BSL
38+
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
39+
; CHECK-NEXT: {{ $}}
40+
; CHECK-NEXT: renamable $q2 = BSLv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
41+
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
42+
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
43+
; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
44+
; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
45+
; CHECK-NEXT: RET undef $lr, implicit $q22
46+
renamable $q2 = BSPv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
47+
$q22 = ORRv16i8 $q0, killed $q0
48+
$q23 = ORRv16i8 $q1, killed $q1
49+
$q24 = ORRv16i8 $q2, killed $q2
50+
$q25 = ORRv16i8 $q3, killed $q3
51+
RET_ReallyLR implicit $q22
52+
...
53+
---
54+
name: BIF
55+
tracksRegLiveness: true
56+
body: |
57+
bb.0.entry:
58+
liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
59+
60+
; CHECK-LABEL: name: BIF
61+
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
62+
; CHECK-NEXT: {{ $}}
63+
; CHECK-NEXT: renamable $q2 = BIFv16i8 renamable $q2, renamable $q6, killed renamable $q20, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
64+
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
65+
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
66+
; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
67+
; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
68+
; CHECK-NEXT: RET undef $lr, implicit $q22
69+
renamable $q2 = BSPv16i8 killed renamable $q20, renamable $q2, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
70+
$q22 = ORRv16i8 $q0, killed $q0
71+
$q23 = ORRv16i8 $q1, killed $q1
72+
$q24 = ORRv16i8 $q2, killed $q2
73+
$q25 = ORRv16i8 $q3, killed $q3
74+
RET_ReallyLR implicit $q22
75+
...
76+
---
77+
name: BIT
78+
tracksRegLiveness: true
79+
body: |
80+
bb.0.entry:
81+
liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
82+
83+
; CHECK-LABEL: name: BIT
84+
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
85+
; CHECK-NEXT: {{ $}}
86+
; CHECK-NEXT: renamable $q2 = BITv16i8 renamable $q2, renamable $q21, killed renamable $q20, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
87+
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
88+
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
89+
; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
90+
; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
91+
; CHECK-NEXT: RET undef $lr, implicit $q22
92+
renamable $q2 = BSPv16i8 killed renamable $q20, renamable $q21, renamable $q2, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
93+
$q22 = ORRv16i8 $q0, killed $q0
94+
$q23 = ORRv16i8 $q1, killed $q1
95+
$q24 = ORRv16i8 $q2, killed $q2
96+
$q25 = ORRv16i8 $q3, killed $q3
97+
RET_ReallyLR implicit $q22
98+
...

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