[AArch64][GlobalISel] Prevented llvm.aarch64.sisd.fcvtxn fallback (#159811)

Added extra check in AArch64RegisterBankInfo.cpp to mark
llvm.aarch64.sisd.fcvtxn as having floating point operands

Author: JoshdRod

llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

@@ -486,6 +486,7 @@ static bool isFPIntrinsic(const MachineRegisterInfo &MRI,
   case Intrinsic::aarch64_crypto_sha1c:
   case Intrinsic::aarch64_crypto_sha1p:
   case Intrinsic::aarch64_crypto_sha1m:
+  case Intrinsic::aarch64_sisd_fcvtxn:
     return true;
   case Intrinsic::aarch64_neon_saddlv: {
     const LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());

llvm/test/CodeGen/AArch64/arm64-vcvtxd_f32_f64.ll

@@ -1,8 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-eabi -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-
-; CHECK-GI:       warning: Instruction selection used fallback path for fcvtxn
+; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s --check-prefixes=CHECK
 
 define float @fcvtxn(double %a) {
 ; CHECK-LABEL: fcvtxn: