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[RISCV][FPEnv] Lowering of fpenv intrinsics (#141498)
The change implements custom lowering of `get_fpenv`, `set_fpenv` and `reset_fpenv` for RISCV target.
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6 files changed

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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -649,6 +649,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::GET_ROUNDING, XLenVT, Custom);
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setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
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setOperationAction(ISD::GET_FPENV, XLenVT, Custom);
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setOperationAction(ISD::SET_FPENV, XLenVT, Custom);
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setOperationAction(ISD::RESET_FPENV, MVT::Other, Custom);
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}
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setOperationAction({ISD::GlobalAddress, ISD::BlockAddress, ISD::ConstantPool,
@@ -8159,6 +8162,12 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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return lowerGET_ROUNDING(Op, DAG);
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case ISD::SET_ROUNDING:
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return lowerSET_ROUNDING(Op, DAG);
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case ISD::GET_FPENV:
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return lowerGET_FPENV(Op, DAG);
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case ISD::SET_FPENV:
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return lowerSET_FPENV(Op, DAG);
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case ISD::RESET_FPENV:
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return lowerRESET_FPENV(Op, DAG);
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case ISD::EH_DWARF_CFA:
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return lowerEH_DWARF_CFA(Op, DAG);
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case ISD::VP_MERGE:
@@ -13799,6 +13808,41 @@ SDValue RISCVTargetLowering::lowerSET_ROUNDING(SDValue Op,
1379913808
RMValue);
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}
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SDValue RISCVTargetLowering::lowerGET_FPENV(SDValue Op,
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SelectionDAG &DAG) const {
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const MVT XLenVT = Subtarget.getXLenVT();
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SDLoc DL(Op);
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SDValue Chain = Op->getOperand(0);
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SDValue SysRegNo = DAG.getTargetConstant(RISCVSysReg::fcsr, DL, XLenVT);
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SDVTList VTs = DAG.getVTList(XLenVT, MVT::Other);
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return DAG.getNode(RISCVISD::READ_CSR, DL, VTs, Chain, SysRegNo);
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}
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SDValue RISCVTargetLowering::lowerSET_FPENV(SDValue Op,
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SelectionDAG &DAG) const {
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const MVT XLenVT = Subtarget.getXLenVT();
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SDLoc DL(Op);
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SDValue Chain = Op->getOperand(0);
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SDValue EnvValue = Op->getOperand(1);
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SDValue SysRegNo = DAG.getTargetConstant(RISCVSysReg::fcsr, DL, XLenVT);
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EnvValue = DAG.getNode(ISD::ZERO_EXTEND, DL, XLenVT, EnvValue);
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return DAG.getNode(RISCVISD::WRITE_CSR, DL, MVT::Other, Chain, SysRegNo,
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EnvValue);
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}
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SDValue RISCVTargetLowering::lowerRESET_FPENV(SDValue Op,
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SelectionDAG &DAG) const {
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const MVT XLenVT = Subtarget.getXLenVT();
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SDLoc DL(Op);
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SDValue Chain = Op->getOperand(0);
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SDValue EnvValue = DAG.getRegister(RISCV::X0, XLenVT);
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SDValue SysRegNo = DAG.getTargetConstant(RISCVSysReg::fcsr, DL, XLenVT);
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return DAG.getNode(RISCVISD::WRITE_CSR, DL, MVT::Other, Chain, SysRegNo,
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EnvValue);
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}
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SDValue RISCVTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
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SelectionDAG &DAG) const {
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MachineFunction &MF = DAG.getMachineFunction();

‎llvm/lib/Target/RISCV/RISCVISelLowering.h‎

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Original file line numberDiff line numberDiff line change
@@ -544,6 +544,9 @@ class RISCVTargetLowering : public TargetLowering {
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unsigned ExtendOpc) const;
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SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerRESET_FPENV(SDValue Op, SelectionDAG &DAG) const;
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548551
SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td‎

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Original file line numberDiff line numberDiff line change
@@ -2037,6 +2037,13 @@ let hasSideEffects = true in {
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def ReadFFLAGS : ReadSysReg<SysRegFFLAGS, [FFLAGS]>;
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def WriteFFLAGS : WriteSysReg<SysRegFFLAGS, [FFLAGS]>;
20392039
}
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2041+
let hasPostISelHook = 1 in {
2042+
def ReadFCSR : ReadSysReg<SysRegFCSR, [FRM, FFLAGS]>;
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def WriteFCSR : WriteSysReg<SysRegFCSR, [FRM, FFLAGS]>;
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def WriteFCSRImm : WriteSysRegImm<SysRegFCSR, [FRM, FFLAGS]>;
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}
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/// Other pseudo-instructions
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// Pessimistically assume the stack pointer will be clobbered

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.td‎

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Original file line numberDiff line numberDiff line change
@@ -846,6 +846,7 @@ foreach m = LMULList in {
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def FFLAGS : RISCVReg<0, "fflags">;
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def FRM : RISCVReg<0, "frm">;
849+
def FCSR : RISCVReg<0, "fcsr">;
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850851
// Shadow Stack register
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def SSP : RISCVReg<0, "ssp">;

‎llvm/test/CodeGen/RISCV/fpenv-xlen.ll‎

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs | FileCheck %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs | FileCheck %s
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs | FileCheck %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs | FileCheck %s
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs -O0 | FileCheck %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs -O0 | FileCheck %s
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9+
define iXLen @func_get_fpenv() {
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; CHECK-LABEL: func_get_fpenv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: frcsr a0
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; CHECK-NEXT: ret
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entry:
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%fpenv = call iXLen @llvm.get.fpenv.iXLen()
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ret iXLen %fpenv
17+
}
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define void @func_set_fpenv(iXLen %fpenv) {
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; CHECK-LABEL: func_set_fpenv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fscsr a0
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; CHECK-NEXT: ret
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entry:
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call void @llvm.set.fpenv.iXLen(iXLen %fpenv)
26+
ret void
27+
}
28+
29+
define void @func_reset_fpenv() {
30+
; CHECK-LABEL: func_reset_fpenv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fscsr zero
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; CHECK-NEXT: ret
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entry:
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call void @llvm.reset.fpenv()
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ret void
37+
}

‎llvm/test/CodeGen/RISCV/frm-write-in-loop.ll‎

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Original file line numberDiff line numberDiff line change
@@ -90,3 +90,34 @@ loop:
9090
exit:
9191
ret double %f2
9292
}
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define double @foo2(double %0, double %1, i64 %n, i64 %fcsr) strictfp {
95+
; CHECK-LABEL: foo2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fmv.d.x fa5, zero
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; CHECK-NEXT: .LBB2_1: # %loop
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: csrwi fcsr, 0
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; CHECK-NEXT: fadd.d fa5, fa5, fa0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: fscsr a1
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; CHECK-NEXT: fadd.d fa5, fa5, fa1
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; CHECK-NEXT: beqz a0, .LBB2_1
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; CHECK-NEXT: # %bb.2: # %exit
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; CHECK-NEXT: fmv.d fa0, fa5
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; CHECK-NEXT: ret
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entry:
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br label %loop
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loop:
112+
%cnt = phi i64 [0, %entry], [%cnt_inc, %loop]
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%acc = phi double [0.0, %entry], [%f2, %loop]
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call void @llvm.set.fpenv(i64 0) strictfp
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%f1 = call double @llvm.experimental.constrained.fadd.f64(double %acc, double %0, metadata !"round.dynamic", metadata !"fpexcept.ignore") strictfp
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call void @llvm.set.fpenv(i64 %fcsr) strictfp
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%f2 = call double @llvm.experimental.constrained.fadd.f64(double %f1, double %1, metadata !"round.dynamic", metadata !"fpexcept.ignore") strictfp
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%cnt_inc = add i64 %cnt, 1
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%cond = icmp eq i64 %cnt_inc, %n
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br i1 %cond, label %loop, label %exit
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exit:
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ret double %f2
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}

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