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[AArch64] Add assembly/disassembly for {S,SU,US,U}MOP4{A,S} instructions (#113349)
The new instructions are described in https://developer.arm.com/documentation/ddi0602/2024-09/SME-Instructions Co-Authored-By: Marian Lukac <[email protected]>
1 parent 73fbae8 commit 95c5042

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‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td‎

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@@ -131,6 +131,33 @@ defm USMOPA_MPPZZ_D : sme_int_outer_product_i64<0b100, "usmopa", int_aarch64_sme
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defm USMOPS_MPPZZ_D : sme_int_outer_product_i64<0b101, "usmops", int_aarch64_sme_usmops_wide>;
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}
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let Predicates = [HasSME2p2] in {
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defm SMOP4A : sme_quarter_outer_product_i8_i32<0b0, 0b0, 0b0, "smop4a">;
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defm SMOP4S : sme_quarter_outer_product_i8_i32<0b0, 0b0, 0b1, "smop4s">;
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defm SUMOP4A : sme_quarter_outer_product_i8_i32<0b0, 0b1, 0b0, "sumop4a">;
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defm SUMOP4S : sme_quarter_outer_product_i8_i32<0b0, 0b1, 0b1, "sumop4s">;
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defm USMOP4A : sme_quarter_outer_product_i8_i32<0b1, 0b0, 0b0, "usmop4a">;
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defm USMOP4S : sme_quarter_outer_product_i8_i32<0b1, 0b0, 0b1, "usmop4s">;
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defm UMOP4A : sme_quarter_outer_product_i8_i32<0b1, 0b1, 0b0, "umop4a">;
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defm UMOP4S : sme_quarter_outer_product_i8_i32<0b1, 0b1, 0b1, "umop4s">;
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defm SMOP4A : sme_quarter_outer_product_i16_i32<0b0, 0b0, "smop4a">;
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defm SMOP4S : sme_quarter_outer_product_i16_i32<0b0, 0b1, "smop4s">;
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defm UMOP4A : sme_quarter_outer_product_i16_i32<0b1, 0b0, "umop4a">;
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defm UMOP4S : sme_quarter_outer_product_i16_i32<0b1, 0b1, "umop4s">;
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}
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let Predicates = [HasSME2p2, HasSMEI16I64] in {
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defm SMOP4A : sme_quarter_outer_product_i64<0b0, 0b0, 0b0, "smop4a">;
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defm SMOP4S : sme_quarter_outer_product_i64<0b0, 0b0, 0b1, "smop4s">;
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defm SUMOP4A : sme_quarter_outer_product_i64<0b0, 0b1, 0b0, "sumop4a">;
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defm SUMOP4S : sme_quarter_outer_product_i64<0b0, 0b1, 0b1, "sumop4s">;
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defm UMOP4A : sme_quarter_outer_product_i64<0b1, 0b1, 0b0, "umop4a">;
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defm UMOP4S : sme_quarter_outer_product_i64<0b1, 0b1, 0b1, "umop4s">;
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defm USMOP4A : sme_quarter_outer_product_i64<0b1, 0b0, 0b0, "usmop4a">;
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defm USMOP4S : sme_quarter_outer_product_i64<0b1, 0b0, 0b1, "usmop4s">;
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}
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let Predicates = [HasSME] in {
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//===----------------------------------------------------------------------===//
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// Loads and stores

‎llvm/lib/Target/AArch64/SMEInstrFormats.td‎

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@@ -433,6 +433,116 @@ multiclass sme_f16_outer_product<bits<3> opc, string mnemonic, SDPatternOperator
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def : SME_ZA_Tile_TwoPred_TwoVec_Pat<NAME, op, timm32_0_3, nxv8i1, nxv8f16>;
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}
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class sme_quarter_outer_product_i64<bits<2> zn_u_pair, bits<2> zm_u_pair, bit subtr, RegisterOperand zn_ty, RegisterOperand zm_ty, string mnemonic>
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: I<(outs TileOp64:$ZAda),
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(ins TileOp64:$_ZAda, zn_ty:$Zn, zm_ty:$Zm),
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mnemonic, "\t$ZAda, $Zn, $Zm",
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"", []>,
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Sched<[]> {
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bits<3> ZAda;
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bits<3> Zn;
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bits<3> Zm;
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let Inst{31-25} = 0b1010000;
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let Inst{24} = zn_u_pair{1}; // u0
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let Inst{23-22} = 0b11;
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let Inst{21} = zm_u_pair{1}; // u1
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let Inst{20} = zm_u_pair{0}; // M
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let Inst{19-17} = Zm;
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let Inst{16-10} = 0b0000000;
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let Inst{9} = zn_u_pair{0}; // N
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let Inst{8-6} = Zn;
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let Inst{5} = 0;
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let Inst{4} = subtr;
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let Inst{3} = 0b1;
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let Inst{2-0} = ZAda;
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let Constraints = "$ZAda = $_ZAda";
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}
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class sme_quarter_outer_product_i8_i32<bits<2> zn_u_pair, bits<2> zm_u_pair, bit subtr, RegisterOperand zn_ty, RegisterOperand zm_ty, string mnemonic>
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: I<(outs TileOp32:$ZAda),
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(ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm),
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mnemonic, "\t$ZAda, $Zn, $Zm",
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"", []>,
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Sched<[]> {
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bits<2> ZAda;
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bits<3> Zn;
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bits<3> Zm;
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let Inst{31-25} = 0b1000000;
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let Inst{24} = zn_u_pair{1}; // u0
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let Inst{23-22} = 0b00;
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let Inst{21} = zm_u_pair{1}; // u1
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let Inst{20} = zm_u_pair{0}; // M
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let Inst{19-17} = Zm;
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let Inst{16-10} = 0b0100000;
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let Inst{9} = zn_u_pair{0}; // N
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let Inst{8-6} = Zn;
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let Inst{5} = 0;
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let Inst{4} = subtr;
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let Inst{3-2} = 0b00;
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let Inst{1-0} = ZAda;
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let Constraints = "$ZAda = $_ZAda";
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}
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class sme_quarter_outer_product_i16_i32<bit u0, bit N, bit M, bit subtr, RegisterOperand zn_ty, RegisterOperand zm_ty, string mnemonic>
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: I<(outs TileOp32:$ZAda),
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(ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm),
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mnemonic, "\t$ZAda, $Zn, $Zm",
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"", []>,
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Sched<[]> {
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bits<2> ZAda;
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bits<3> Zn;
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bits<3> Zm;
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let Inst{31-25} = 0b1000000;
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let Inst{24} = u0;
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let Inst{23-21} = 0b000;
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let Inst{20} = M;
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let Inst{19-17} = Zm;
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let Inst{16-10} = 0b0100000;
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let Inst{9} = N;
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let Inst{8-6} = Zn;
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let Inst{5} = 0;
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let Inst{4} = subtr;
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let Inst{3-2} = 0b10;
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let Inst{1-0} = ZAda;
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let Constraints = "$ZAda = $_ZAda";
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}
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multiclass sme_quarter_outer_product_i8_i32<bit zn_u, bit zm_u, bit subtr, string mnemonic>{
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def _MZZ_BToS : sme_quarter_outer_product_i8_i32<{zn_u, 0}, {zm_u, 0}, subtr,
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ZPR8Mul2_Lo, ZPR8Mul2_Hi, mnemonic>;
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def _M2ZZ_BToS : sme_quarter_outer_product_i8_i32<{zn_u, 1}, {zm_u, 0}, subtr,
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ZZ_b_mul_r_Lo, ZPR8Mul2_Hi, mnemonic>;
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def _MZ2Z_BToS : sme_quarter_outer_product_i8_i32<{zn_u, 0}, {zm_u, 1}, subtr,
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ZPR8Mul2_Lo, ZZ_b_mul_r_Hi, mnemonic>;
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def _M2Z2Z_BToS : sme_quarter_outer_product_i8_i32<{zn_u, 1}, {zm_u, 1}, subtr,
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ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi, mnemonic>;
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}
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multiclass sme_quarter_outer_product_i16_i32<bit unsigned, bit subtr, string mnemonic>{
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def _MZZ_HToS : sme_quarter_outer_product_i16_i32<unsigned, 0b0, 0b0, subtr,
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ZPR16Mul2_Lo, ZPR16Mul2_Hi, mnemonic>;
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def _M2ZZ_HToS : sme_quarter_outer_product_i16_i32<unsigned, 0b1, 0b0, subtr,
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ZZ_h_mul_r_Lo, ZPR16Mul2_Hi, mnemonic>;
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def _MZ2Z_HToS : sme_quarter_outer_product_i16_i32<unsigned, 0b0, 0b1, subtr,
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ZPR16Mul2_Lo, ZZ_h_mul_r_Hi, mnemonic>;
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def _M2Z2Z_HToS : sme_quarter_outer_product_i16_i32<unsigned, 0b1, 0b1, subtr,
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ZZ_h_mul_r_Lo, ZZ_h_mul_r_Hi, mnemonic>;
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}
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multiclass sme_quarter_outer_product_i64<bit zn_u, bit zm_u, bit subtr, string mnemonic>{
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def _MZZ_HtoD : sme_quarter_outer_product_i64<{zn_u, 0}, {zm_u, 0}, subtr,
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ZPR16Mul2_Lo, ZPR16Mul2_Hi, mnemonic>;
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def _M2ZZ_HtoD : sme_quarter_outer_product_i64<{zn_u, 1}, {zm_u, 0}, subtr,
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ZZ_h_mul_r_Lo, ZPR16Mul2_Hi, mnemonic>;
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def _MZ2Z_HtoD : sme_quarter_outer_product_i64<{zn_u, 0}, {zm_u, 1}, subtr,
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ZPR16Mul2_Lo, ZZ_h_mul_r_Hi, mnemonic>;
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def _M2Z2Z_HtoD : sme_quarter_outer_product_i64<{zn_u, 1}, {zm_u, 1}, subtr,
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ZZ_h_mul_r_Lo, ZZ_h_mul_r_Hi, mnemonic>;
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}
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//===----------------------------------------------------------------------===//
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// SME Add Vector to Tile
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//===----------------------------------------------------------------------===//

‎llvm/test/MC/AArch64/SME2p2/smop4a-16to32.s‎

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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smop4a za0.s, z0.h, z16.h // 10000000-00000000-10000000-00001000
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// CHECK-INST: smop4a za0.s, z0.h, z16.h
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// CHECK-ENCODING: [0x08,0x80,0x00,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 80008008 <unknown>
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smop4a za3.s, z12.h, z24.h // 10000000-00001000-10000001-10001011
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// CHECK-INST: smop4a za3.s, z12.h, z24.h
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// CHECK-ENCODING: [0x8b,0x81,0x08,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 8008818b <unknown>
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smop4a za3.s, z14.h, z30.h // 10000000-00001110-10000001-11001011
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// CHECK-INST: smop4a za3.s, z14.h, z30.h
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// CHECK-ENCODING: [0xcb,0x81,0x0e,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 800e81cb <unknown>
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smop4a za0.s, z0.h, {z16.h-z17.h} // 10000000-00010000-10000000-00001000
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// CHECK-INST: smop4a za0.s, z0.h, { z16.h, z17.h }
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// CHECK-ENCODING: [0x08,0x80,0x10,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 80108008 <unknown>
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smop4a za3.s, z12.h, {z24.h-z25.h} // 10000000-00011000-10000001-10001011
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// CHECK-INST: smop4a za3.s, z12.h, { z24.h, z25.h }
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// CHECK-ENCODING: [0x8b,0x81,0x18,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 8018818b <unknown>
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smop4a za3.s, z14.h, {z30.h-z31.h} // 10000000-00011110-10000001-11001011
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// CHECK-INST: smop4a za3.s, z14.h, { z30.h, z31.h }
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// CHECK-ENCODING: [0xcb,0x81,0x1e,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 801e81cb <unknown>
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smop4a za0.s, {z0.h-z1.h}, z16.h // 10000000-00000000-10000010-00001000
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// CHECK-INST: smop4a za0.s, { z0.h, z1.h }, z16.h
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// CHECK-ENCODING: [0x08,0x82,0x00,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 80008208 <unknown>
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smop4a za3.s, {z12.h-z13.h}, z24.h // 10000000-00001000-10000011-10001011
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// CHECK-INST: smop4a za3.s, { z12.h, z13.h }, z24.h
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// CHECK-ENCODING: [0x8b,0x83,0x08,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 8008838b <unknown>
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smop4a za3.s, {z14.h-z15.h}, z30.h // 10000000-00001110-10000011-11001011
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// CHECK-INST: smop4a za3.s, { z14.h, z15.h }, z30.h
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// CHECK-ENCODING: [0xcb,0x83,0x0e,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 800e83cb <unknown>
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smop4a za0.s, {z0.h-z1.h}, {z16.h-z17.h} // 10000000-00010000-10000010-00001000
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// CHECK-INST: smop4a za0.s, { z0.h, z1.h }, { z16.h, z17.h }
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// CHECK-ENCODING: [0x08,0x82,0x10,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 80108208 <unknown>
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smop4a za3.s, {z12.h-z13.h}, {z24.h-z25.h} // 10000000-00011000-10000011-10001011
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// CHECK-INST: smop4a za3.s, { z12.h, z13.h }, { z24.h, z25.h }
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// CHECK-ENCODING: [0x8b,0x83,0x18,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 8018838b <unknown>
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smop4a za3.s, {z14.h-z15.h}, {z30.h-z31.h} // 10000000-00011110-10000011-11001011
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// CHECK-INST: smop4a za3.s, { z14.h, z15.h }, { z30.h, z31.h }
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// CHECK-ENCODING: [0xcb,0x83,0x1e,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 801e83cb <unknown>

‎llvm/test/MC/AArch64/SME2p2/smop4a-64.s‎

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \
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// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \
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// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-i16i64 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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smop4a za0.d, z0.h, z16.h // 10100000-11000000-00000000-00001000
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// CHECK-INST: smop4a za0.d, z0.h, z16.h
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// CHECK-ENCODING: [0x08,0x00,0xc0,0xa0]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: a0c00008 <unknown>
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smop4a za5.d, z10.h, z20.h // 10100000-11000100-00000001-01001101
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// CHECK-INST: smop4a za5.d, z10.h, z20.h
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// CHECK-ENCODING: [0x4d,0x01,0xc4,0xa0]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: a0c4014d <unknown>
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smop4a za7.d, z14.h, z30.h // 10100000-11001110-00000001-11001111
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// CHECK-INST: smop4a za7.d, z14.h, z30.h
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// CHECK-ENCODING: [0xcf,0x01,0xce,0xa0]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: a0ce01cf <unknown>
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smop4a za0.d, z0.h, {z16.h-z17.h} // 10100000-11010000-00000000-00001000
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// CHECK-INST: smop4a za0.d, z0.h, { z16.h, z17.h }
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// CHECK-ENCODING: [0x08,0x00,0xd0,0xa0]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: a0d00008 <unknown>
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smop4a za5.d, z10.h, {z20.h-z21.h} // 10100000-11010100-00000001-01001101
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// CHECK-INST: smop4a za5.d, z10.h, { z20.h, z21.h }
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// CHECK-ENCODING: [0x4d,0x01,0xd4,0xa0]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: a0d4014d <unknown>
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smop4a za7.d, z14.h, {z30.h-z31.h} // 10100000-11011110-00000001-11001111
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// CHECK-INST: smop4a za7.d, z14.h, { z30.h, z31.h }
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// CHECK-ENCODING: [0xcf,0x01,0xde,0xa0]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: a0de01cf <unknown>
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smop4a za0.d, {z0.h-z1.h}, z16.h // 10100000-11000000-00000010-00001000
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// CHECK-INST: smop4a za0.d, { z0.h, z1.h }, z16.h
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// CHECK-ENCODING: [0x08,0x02,0xc0,0xa0]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: a0c00208 <unknown>
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smop4a za5.d, {z10.h-z11.h}, z20.h // 10100000-11000100-00000011-01001101
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// CHECK-INST: smop4a za5.d, { z10.h, z11.h }, z20.h
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// CHECK-ENCODING: [0x4d,0x03,0xc4,0xa0]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: a0c4034d <unknown>
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smop4a za7.d, {z14.h-z15.h}, z30.h // 10100000-11001110-00000011-11001111
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// CHECK-INST: smop4a za7.d, { z14.h, z15.h }, z30.h
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// CHECK-ENCODING: [0xcf,0x03,0xce,0xa0]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: a0ce03cf <unknown>
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smop4a za0.d, {z0.h-z1.h}, {z16.h-z17.h} // 10100000-11010000-00000010-00001000
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// CHECK-INST: smop4a za0.d, { z0.h, z1.h }, { z16.h, z17.h }
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// CHECK-ENCODING: [0x08,0x02,0xd0,0xa0]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: a0d00208 <unknown>
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smop4a za5.d, {z10.h-z11.h}, {z20.h-z21.h} // 10100000-11010100-00000011-01001101
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// CHECK-INST: smop4a za5.d, { z10.h, z11.h }, { z20.h, z21.h }
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// CHECK-ENCODING: [0x4d,0x03,0xd4,0xa0]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: a0d4034d <unknown>
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smop4a za7.d, {z14.h-z15.h}, {z30.h-z31.h} // 10100000-11011110-00000011-11001111
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// CHECK-INST: smop4a za7.d, { z14.h, z15.h }, { z30.h, z31.h }
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// CHECK-ENCODING: [0xcf,0x03,0xde,0xa0]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: a0de03cf <unknown>

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