Add Ziccamoc 2.0

Author: Tie

clang/test/Driver/print-supported-extensions-riscv.c

@@ -19,6 +19,7 @@
 // CHECK-NEXT:     zicbop               1.0       'Zicbop' (Cache-Block Prefetch Instructions)
 // CHECK-NEXT:     zicboz               1.0       'Zicboz' (Cache-Block Zero Instructions)
 // CHECK-NEXT:     ziccamoa             1.0       'Ziccamoa' (Main Memory Supports All Atomics in A)
+// CHECK-NEXT:     ziccamoc             1.0       'Ziccamoc' (Main Memory Supports Atomics in Zacas)
 // CHECK-NEXT:     ziccif               1.0       'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)
 // CHECK-NEXT:     zicclsm              1.0       'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)
 // CHECK-NEXT:     ziccrse              1.0       'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)

clang/test/Preprocessor/riscv-target-features.c

@@ -1051,7 +1051,6 @@
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32iziccamoc -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICCAMOC-EXT %s
-// CHECK-ZICCAMOC-EXT: __riscv_ziccamoc 1000000{{$}}
 // RUN: %clang --target=riscv64-unknown-linux-gnu \
 // RUN:   -march=rv64iziccamoc -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICCAMOC-EXT %s

llvm/docs/ReleaseNotes.md

@@ -167,9 +167,11 @@ Changes to the RISC-V Backend
 * Adds assembler support for ``.option exact``, which disables automatic compression,
   and branch and linker relaxation. This can be disabled with ``.option noexact``,
   which is also the default.
+<<<<<<< HEAD
 * `-mcpu=xiangshan-kunminghu` was added.
 * `-mcpu=andes-n45` and `-mcpu=andes-nx45` were added.
 * `-mcpu=andes-a45` and `-mcpu=andes-ax45` were added.
+* Adds support for the 'Ziccamoc` (Main Memory Supports Atomics in Zacas) extension, which was introduced as an optional extension of the RISC-V Profiles specification.
 
 Changes to the WebAssembly Backend
 ----------------------------------

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -103,7 +103,7 @@ def FeatureStdExtZiccamoa
     : RISCVExtension<1, 0, "Main Memory Supports All Atomics in A">;
 
 def FeatureStdExtZiccamoc
-    : RISCVExtension<1, 0, "Main memory supports atomics in Zacas">;
+    : RISCVExtension<1, 0, "Main Memory Supports Atomics in Zacas">;
 
 def FeatureStdExtZiccif
     : RISCVExtension<1, 0,

llvm/test/CodeGen/RISCV/features-info.ll

@@ -237,6 +237,7 @@
 ; CHECK-NEXT:   zicbop                           - 'Zicbop' (Cache-Block Prefetch Instructions).
 ; CHECK-NEXT:   zicboz                           - 'Zicboz' (Cache-Block Zero Instructions).
 ; CHECK-NEXT:   ziccamoa                         - 'Ziccamoa' (Main Memory Supports All Atomics in A).
+; CHECK-NEXT:   ziccamoc                         - 'Ziccamoc' (Main Memory Supports Atomics in Zacas).
 ; CHECK-NEXT:   ziccif                           - 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement).
 ; CHECK-NEXT:   zicclsm                          - 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores).
 ; CHECK-NEXT:   ziccrse                          - 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences).