[X86] Changes made for code review comments

Author: GrumpyPigSkin

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -23637,43 +23637,47 @@ static SDValue EmitTest(SDValue Op, X86::CondCode X86CC, const SDLoc &dl,
     // If optimising for size and can guarantee the shift amt is never zero
     // the test.
     bool OptForSize = DAG.getMachineFunction().getFunction().hasOptSize();
-    if (OptForSize && DAG.isKnownNeverZero(Amt)) {
-      SDLoc DL(ArithOp);
 
-      // CopyToReg(CL, Amt)
-      SDValue Chain = DAG.getEntryNode();
-      SDValue Glue;
+    if (!OptForSize)
+      break;
 
-      Chain = DAG.getCopyToReg(Chain, DL, X86::CL, Amt, Glue);
-      Glue = Chain.getValue(1);
+    if (!DAG.isKnownNeverZero(Amt))
+      break;
 
-      // Select Opcode
-      unsigned X86Opcode;
-      switch (ArithOp.getOpcode()) {
-      case ISD::SHL:
-        X86Opcode = X86ISD::SHL;
-        break;
-      case ISD::SRL:
-        X86Opcode = X86ISD::SRL;
-        break;
-      case ISD::SRA:
-        X86Opcode = X86ISD::SRA;
-        break;
-      default:
-        llvm_unreachable("Unexpected shift opcode");
-      }
+    SDLoc DL(ArithOp);
 
-      // Create Node [ValueToShift, Glue]
-      SDVTList VTs = DAG.getVTList(ArithOp.getValueType(), MVT::i32);
-      SDValue Ops[] = {ArithOp.getOperand(0), Glue};
+    // CopyToReg(CL, Amt)
+    SDValue Chain = DAG.getEntryNode();
+    SDValue Glue;
 
-      SDValue NewNode = DAG.getNode(X86Opcode, DL, VTs, Ops);
+    Chain = DAG.getCopyToReg(Chain, DL, X86::CL, Amt, Glue);
+    Glue = Chain.getValue(1);
 
-      // Replace and Return
-      DAG.ReplaceAllUsesOfValueWith(ArithOp, NewNode.getValue(0));
-      return NewNode.getValue(1);
+    // Select Opcode
+    unsigned X86Opcode;
+    switch (ArithOp.getOpcode()) {
+    case ISD::SHL:
+      X86Opcode = X86ISD::SHL;
+      break;
+    case ISD::SRL:
+      X86Opcode = X86ISD::SRL;
+      break;
+    case ISD::SRA:
+      X86Opcode = X86ISD::SRA;
+      break;
+    default:
+      llvm_unreachable("Unexpected shift opcode");
     }
-    break;
+
+    // Create Node [ValueToShift, Glue]
+    SDVTList VTs = DAG.getVTList(ArithOp.getValueType(), MVT::i32);
+    SDValue Ops[] = {ArithOp.getOperand(0), Glue};
+
+    SDValue NewNode = DAG.getNode(X86Opcode, DL, VTs, Ops);
+
+    // Replace and Return
+    DAG.ReplaceAllUsesOfValueWith(ArithOp, NewNode.getValue(0));
+    return NewNode.getValue(1);
   }
   default:
     break;

llvm/lib/Target/X86/X86ISelLowering.h

@@ -425,6 +425,9 @@ namespace llvm {
     OR,
     XOR,
     AND,
+    SHL,
+    SRL,
+    SRA,
 
     // Bit field extract.
     BEXTR,
@@ -996,9 +999,6 @@ namespace llvm {
     CLOAD,
     CSTORE,
     LAST_MEMORY_OPCODE = CSTORE,
-    SHL,
-    SRL,
-    SRA,
   };
   } // end namespace X86ISD
 

llvm/lib/Target/X86/X86InstrFragments.td

@@ -276,6 +276,15 @@ def X86xor_flag  : SDNode<"X86ISD::XOR",  SDTBinaryArithWithFlags,
 def X86and_flag  : SDNode<"X86ISD::AND",  SDTBinaryArithWithFlags,
                           [SDNPCommutative]>;
 
+def SDTX86ShiftWithFlags : SDTypeProfile<2, 1, [
+  SDTCisSameAs<0, 2>,
+  SDTCisVT<1, i32>,
+]>;
+
+def X86shl : SDNode<"X86ISD::SHL", SDTX86ShiftWithFlags, [SDNPInGlue]>;
+def X86srl : SDNode<"X86ISD::SRL", SDTX86ShiftWithFlags, [SDNPInGlue]>;
+def X86sra : SDNode<"X86ISD::SRA", SDTX86ShiftWithFlags, [SDNPInGlue]>;
+
 def X86lock_add  : SDNode<"X86ISD::LADD",  SDTLockBinaryArithWithFlags,
                           [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
                            SDNPMemOperand]>;

llvm/lib/Target/X86/X86InstrShiftRotate.td

@@ -690,15 +690,6 @@ let Predicates = [HasBMI2, HasEGPR] in {
   defm SHLX : ShiftX_Pats<shl, "_EVEX">;
 }
 
-def SDTX86ShiftWithFlags : SDTypeProfile<2, 1, [
-  SDTCisSameAs<0, 2>,
-  SDTCisVT<1, i32>,
-]>;
-
-def X86shl : SDNode<"X86ISD::SHL", SDTX86ShiftWithFlags, [SDNPInGlue]>;
-def X86srl : SDNode<"X86ISD::SRL", SDTX86ShiftWithFlags, [SDNPInGlue]>;
-def X86sra : SDNode<"X86ISD::SRA", SDTX86ShiftWithFlags, [SDNPInGlue]>;
-
 let Predicates = [NoNDD] in {
   // SHL
   def : Pat<(X86shl GR8:$src1),  (SHL8rCL  GR8:$src1)>;