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Merge branch 'main' into sve-fmmla
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‎flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -511,6 +511,11 @@ DebugTypeGenerator::convertType(mlir::Type Ty, mlir::LLVM::DIFileAttr fileAttr,
511511
/*hasDescriptor=*/false);
512512
} else if (auto recTy = mlir::dyn_cast_or_null<fir::RecordType>(Ty)) {
513513
return convertRecordType(recTy, fileAttr, scope, declOp);
514+
} else if (auto refTy = mlir::dyn_cast_if_present<fir::ReferenceType>(Ty)) {
515+
auto elTy = refTy.getEleTy();
516+
return convertPointerLikeType(elTy, fileAttr, scope, declOp,
517+
/*genAllocated=*/false,
518+
/*genAssociated=*/false);
514519
} else if (auto boxTy = mlir::dyn_cast_or_null<fir::BoxType>(Ty)) {
515520
auto elTy = boxTy.getElementType();
516521
if (auto seqTy = mlir::dyn_cast_or_null<fir::SequenceType>(elTy))

‎flang/test/Transforms/debug-ref-type.fir‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
// RUN: fir-opt --add-debug-info --mlir-print-debuginfo %s | FileCheck %s
2+
3+
module attributes {dlti.dl_spec = #dlti.dl_spec<>} {
4+
func.func private @_FortranAioBeginExternalListOutput(i8) -> !fir.ref<i8> loc(#loc1)
5+
}
6+
#loc1 = loc("test.f90":5:1)
7+
8+
// CHECK: #[[INT8_TY:.*]] = #llvm.di_basic_type<tag = DW_TAG_base_type, name = "integer", sizeInBits = 8, encoding = DW_ATE_signed>
9+
// CHECK: #[[REF_TY:.*]] = #llvm.di_derived_type<tag = DW_TAG_pointer_type, name = "", baseType = #[[INT8_TY]]{{.*}}>
10+
// CHECK: #llvm.di_subroutine_type<{{.*}}types = #[[REF_TY]], #[[INT8_TY]]>

‎llvm/docs/ReleaseNotes.md‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -268,6 +268,10 @@ Changes to the LLVM tools
268268
Changes to LLDB
269269
---------------------------------
270270

271+
* LLDB can now read the `fpmr` register from AArch64 Linux processes and core
272+
files.
273+
274+
271275
Changes to BOLT
272276
---------------------------------
273277

‎llvm/lib/Target/AArch64/AArch64Features.td‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -526,23 +526,23 @@ def FeatureCMPBR : ExtensionWithMArch<"cmpbr", "CMPBR", "FEAT_CMPBR",
526526
"Enable Armv9.6-A base compare and branch instructions">;
527527

528528
def FeatureF8F32MM: ExtensionWithMArch<"f8f32mm", "F8F32MM", "FEAT_F8F32MM",
529-
"Enable Armv9.6-A FP8 to Single-Precision Matrix Multiplication">;
529+
"Enable Armv9.6-A FP8 to Single-Precision Matrix Multiplication", [FeatureNEON, FeatureFP8]>;
530530

531531
def FeatureF8F16MM: ExtensionWithMArch<"f8f16mm", "F8F16MM", "FEAT_F8F16MM",
532-
"Enable Armv9.6-A FP8 to Half-Precision Matrix Multiplication">;
532+
"Enable Armv9.6-A FP8 to Half-Precision Matrix Multiplication", [FeatureNEON, FeatureFP8]>;
533533

534534
def FeatureFPRCVT: ExtensionWithMArch<"fprcvt", "FPRCVT", "FEAT_FPRCVT",
535535
"Enable Armv9.6-A base convert instructions for SIMD&FP scalar register operands of"
536-
" different input and output sizes">;
536+
" different input and output sizes", [FeatureFPARMv8]>;
537537

538538
def FeatureLSFE : ExtensionWithMArch<"lsfe", "LSFE", "FEAT_LSFE",
539-
"Enable Armv9.6-A base Atomic floating-point in-memory instructions">;
539+
"Enable Armv9.6-A base Atomic floating-point in-memory instructions", [FeatureFPARMv8]>;
540540

541541
def FeatureSME2p2: ExtensionWithMArch<"sme2p2", "SME2p2", "FEAT_SME2p2",
542542
"Enable Armv9.6-A Scalable Matrix Extension 2.2 instructions", [FeatureSME2p1]>;
543543

544544
def FeatureSSVE_AES : ExtensionWithMArch<"ssve-aes", "SSVE_AES", "FEAT_SSVE_AES",
545-
"Enable Armv9.6-A SVE2 AES support in streaming SVE mode">;
545+
"Enable Armv9.6-A SVE2 AES support in streaming SVE mode", [FeatureSME2, FeatureSVE2AES]>;
546546

547547
def FeatureSVE2p2 : ExtensionWithMArch<"sve2p2", "SVE2p2", "FEAT_SVE2p2",
548548
"Enable Armv9.6-A Scalable Vector Extension 2.2 instructions", [FeatureSVE2p1]>;
@@ -554,7 +554,8 @@ def FeatureSVEBFSCALE: ExtensionWithMArch<"sve-bfscale", "SVE_BFSCALE", "FEAT_SV
554554
"Enable Armv9.6-A SVE BFloat16 scaling instructions">;
555555

556556
def FeatureSVE_F16F32MM: ExtensionWithMArch<"sve-f16f32mm", "SVE_F16F32MM", "FEAT_SVE_F16F32MM",
557-
"Enable Armv9.6-A FP16 to FP32 Matrix Multiply instructions">;
557+
"Enable Armv9.6-A FP16 to FP32 Matrix Multiply instructions", [FeatureSVE]>;
558+
558559
def FeatureLSUI: ExtensionWithMArch<"lsui", "LSUI", "FEAT_LSUI",
559560
"Enable Armv9.6-A unprivileged load/store instructions">;
560561

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -287,6 +287,10 @@ def HasSMEF16F16orSMEF8F16
287287
def HasNEONandIsStreamingSafe
288288
: Predicate<"Subtarget->hasNEON()">,
289289
AssemblerPredicateWithAll<(any_of FeatureNEON), "neon">;
290+
// A subset of NEON instructions are legal in Streaming SVE mode only with +sme2p2.
291+
def HasNEONandIsSME2p2StreamingSafe
292+
: Predicate<"Subtarget->isNeonAvailable() || (Subtarget->hasNEON() && Subtarget->hasSME2p2())">,
293+
AssemblerPredicateWithAll<(any_of FeatureNEON), "neon">;
290294
def HasRCPC : Predicate<"Subtarget->hasRCPC()">,
291295
AssemblerPredicateWithAll<(all_of FeatureRCPC), "rcpc">;
292296
def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">,
@@ -6315,8 +6319,7 @@ def : Pat<(v2f64 (AArch64frsqrts (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))),
63156319
// Some float -> int -> float conversion patterns for which we want to keep the
63166320
// int values in FP registers using the corresponding NEON instructions to
63176321
// avoid more costly int <-> fp register transfers.
6318-
// TODO: Allow these in streaming[-compatible] functions with +sme2p2.
6319-
let Predicates = [HasNEON] in {
6322+
let Predicates = [HasNEONandIsSME2p2StreamingSafe] in {
63206323
def : Pat<(f64 (any_sint_to_fp (i64 (any_fp_to_sint f64:$Rn)))),
63216324
(SCVTFv1i64 (i64 (FCVTZSv1i64 f64:$Rn)))>;
63226325
def : Pat<(f32 (any_sint_to_fp (i32 (any_fp_to_sint f32:$Rn)))),
@@ -6326,8 +6329,7 @@ def : Pat<(f64 (any_uint_to_fp (i64 (any_fp_to_uint f64:$Rn)))),
63266329
def : Pat<(f32 (any_uint_to_fp (i32 (any_fp_to_uint f32:$Rn)))),
63276330
(UCVTFv1i32 (i32 (FCVTZUv1i32 f32:$Rn)))>;
63286331

6329-
// TODO: Allow these in streaming[-compatible] functions with +sme2p2.
6330-
let Predicates = [HasNEON, HasFullFP16] in {
6332+
let Predicates = [HasNEONandIsSME2p2StreamingSafe, HasFullFP16] in {
63316333
def : Pat<(f16 (any_sint_to_fp (i32 (any_fp_to_sint f16:$Rn)))),
63326334
(SCVTFv1i16 (f16 (FCVTZSv1f16 f16:$Rn)))>;
63336335
def : Pat<(f16 (any_uint_to_fp (i32 (any_fp_to_uint f16:$Rn)))),
@@ -6350,8 +6352,7 @@ def : Pat<(f64 (uint_to_fp (i64 (vector_extract (v2i64 FPR128:$Rn), (i64 0))))),
63506352

63516353
// fp16: integer extraction from vector must be at least 32-bits to be legal.
63526354
// Actual extraction result is then an in-reg sign-extension of lower 16-bits.
6353-
// TODO: Allow these in streaming[-compatible] functions with +sme2p2.
6354-
let Predicates = [HasNEON, HasFullFP16] in {
6355+
let Predicates = [HasNEONandIsSME2p2StreamingSafe, HasFullFP16] in {
63556356
def : Pat<(f16 (sint_to_fp (i32 (sext_inreg (i32 (vector_extract
63566357
(v8i16 FPR128:$Rn), (i64 0))), i16)))),
63576358
(SCVTFv1i16 (f16 (EXTRACT_SUBREG (v8i16 FPR128:$Rn), hsub)))>;

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll‎

Lines changed: 36 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -force-streaming-compatible < %s | FileCheck %s
3-
; RUN: llc < %s | FileCheck %s --check-prefix=NON-STREAMING
3+
; RUN: llc -force-streaming-compatible -mattr=+sme2p2 < %s | FileCheck %s --check-prefix=USE-NEON-NO-GPRS
4+
; RUN: llc < %s | FileCheck %s --check-prefix=USE-NEON-NO-GPRS
45

56
target triple = "aarch64-unknown-linux-gnu"
67

@@ -11,11 +12,11 @@ define double @t1(double %x) {
1112
; CHECK-NEXT: scvtf d0, x8
1213
; CHECK-NEXT: ret
1314
;
14-
; NON-STREAMING-LABEL: t1:
15-
; NON-STREAMING: // %bb.0: // %entry
16-
; NON-STREAMING-NEXT: fcvtzs d0, d0
17-
; NON-STREAMING-NEXT: scvtf d0, d0
18-
; NON-STREAMING-NEXT: ret
15+
; USE-NEON-NO-GPRS-LABEL: t1:
16+
; USE-NEON-NO-GPRS: // %bb.0: // %entry
17+
; USE-NEON-NO-GPRS-NEXT: fcvtzs d0, d0
18+
; USE-NEON-NO-GPRS-NEXT: scvtf d0, d0
19+
; USE-NEON-NO-GPRS-NEXT: ret
1920
entry:
2021
%conv = fptosi double %x to i64
2122
%conv1 = sitofp i64 %conv to double
@@ -29,11 +30,11 @@ define float @t2(float %x) {
2930
; CHECK-NEXT: scvtf s0, w8
3031
; CHECK-NEXT: ret
3132
;
32-
; NON-STREAMING-LABEL: t2:
33-
; NON-STREAMING: // %bb.0: // %entry
34-
; NON-STREAMING-NEXT: fcvtzs s0, s0
35-
; NON-STREAMING-NEXT: scvtf s0, s0
36-
; NON-STREAMING-NEXT: ret
33+
; USE-NEON-NO-GPRS-LABEL: t2:
34+
; USE-NEON-NO-GPRS: // %bb.0: // %entry
35+
; USE-NEON-NO-GPRS-NEXT: fcvtzs s0, s0
36+
; USE-NEON-NO-GPRS-NEXT: scvtf s0, s0
37+
; USE-NEON-NO-GPRS-NEXT: ret
3738
entry:
3839
%conv = fptosi float %x to i32
3940
%conv1 = sitofp i32 %conv to float
@@ -49,13 +50,13 @@ define half @t3(half %x) {
4950
; CHECK-NEXT: fcvt h0, s0
5051
; CHECK-NEXT: ret
5152
;
52-
; NON-STREAMING-LABEL: t3:
53-
; NON-STREAMING: // %bb.0: // %entry
54-
; NON-STREAMING-NEXT: fcvt s0, h0
55-
; NON-STREAMING-NEXT: fcvtzs s0, s0
56-
; NON-STREAMING-NEXT: scvtf s0, s0
57-
; NON-STREAMING-NEXT: fcvt h0, s0
58-
; NON-STREAMING-NEXT: ret
53+
; USE-NEON-NO-GPRS-LABEL: t3:
54+
; USE-NEON-NO-GPRS: // %bb.0: // %entry
55+
; USE-NEON-NO-GPRS-NEXT: fcvt s0, h0
56+
; USE-NEON-NO-GPRS-NEXT: fcvtzs s0, s0
57+
; USE-NEON-NO-GPRS-NEXT: scvtf s0, s0
58+
; USE-NEON-NO-GPRS-NEXT: fcvt h0, s0
59+
; USE-NEON-NO-GPRS-NEXT: ret
5960
entry:
6061
%conv = fptosi half %x to i32
6162
%conv1 = sitofp i32 %conv to half
@@ -69,11 +70,11 @@ define double @t4(double %x) {
6970
; CHECK-NEXT: ucvtf d0, x8
7071
; CHECK-NEXT: ret
7172
;
72-
; NON-STREAMING-LABEL: t4:
73-
; NON-STREAMING: // %bb.0: // %entry
74-
; NON-STREAMING-NEXT: fcvtzu d0, d0
75-
; NON-STREAMING-NEXT: ucvtf d0, d0
76-
; NON-STREAMING-NEXT: ret
73+
; USE-NEON-NO-GPRS-LABEL: t4:
74+
; USE-NEON-NO-GPRS: // %bb.0: // %entry
75+
; USE-NEON-NO-GPRS-NEXT: fcvtzu d0, d0
76+
; USE-NEON-NO-GPRS-NEXT: ucvtf d0, d0
77+
; USE-NEON-NO-GPRS-NEXT: ret
7778
entry:
7879
%conv = fptoui double %x to i64
7980
%conv1 = uitofp i64 %conv to double
@@ -87,11 +88,11 @@ define float @t5(float %x) {
8788
; CHECK-NEXT: ucvtf s0, w8
8889
; CHECK-NEXT: ret
8990
;
90-
; NON-STREAMING-LABEL: t5:
91-
; NON-STREAMING: // %bb.0: // %entry
92-
; NON-STREAMING-NEXT: fcvtzu s0, s0
93-
; NON-STREAMING-NEXT: ucvtf s0, s0
94-
; NON-STREAMING-NEXT: ret
91+
; USE-NEON-NO-GPRS-LABEL: t5:
92+
; USE-NEON-NO-GPRS: // %bb.0: // %entry
93+
; USE-NEON-NO-GPRS-NEXT: fcvtzu s0, s0
94+
; USE-NEON-NO-GPRS-NEXT: ucvtf s0, s0
95+
; USE-NEON-NO-GPRS-NEXT: ret
9596
entry:
9697
%conv = fptoui float %x to i32
9798
%conv1 = uitofp i32 %conv to float
@@ -107,13 +108,13 @@ define half @t6(half %x) {
107108
; CHECK-NEXT: fcvt h0, s0
108109
; CHECK-NEXT: ret
109110
;
110-
; NON-STREAMING-LABEL: t6:
111-
; NON-STREAMING: // %bb.0: // %entry
112-
; NON-STREAMING-NEXT: fcvt s0, h0
113-
; NON-STREAMING-NEXT: fcvtzu s0, s0
114-
; NON-STREAMING-NEXT: ucvtf s0, s0
115-
; NON-STREAMING-NEXT: fcvt h0, s0
116-
; NON-STREAMING-NEXT: ret
111+
; USE-NEON-NO-GPRS-LABEL: t6:
112+
; USE-NEON-NO-GPRS: // %bb.0: // %entry
113+
; USE-NEON-NO-GPRS-NEXT: fcvt s0, h0
114+
; USE-NEON-NO-GPRS-NEXT: fcvtzu s0, s0
115+
; USE-NEON-NO-GPRS-NEXT: ucvtf s0, s0
116+
; USE-NEON-NO-GPRS-NEXT: fcvt h0, s0
117+
; USE-NEON-NO-GPRS-NEXT: ret
117118
entry:
118119
%conv = fptoui half %x to i32
119120
%conv1 = uitofp i32 %conv to half

‎llvm/unittests/TargetParser/TargetParserTest.cpp‎

Lines changed: 40 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1782,7 +1782,15 @@ AArch64ExtensionDependenciesBaseArchTestParams
17821782
{AArch64::ARMV8A, {"nofp", "jscvt"}, {"fp-armv8", "jsconv"}, {}},
17831783
{AArch64::ARMV8A, {"jscvt", "nofp"}, {}, {"fp-armv8", "jsconv"}},
17841784

1785-
// simd -> {aes, sha2, sha3, sm4}
1785+
// fp -> lsfe
1786+
{AArch64::ARMV9_6A, {"nofp", "lsfe"}, {"fp-armv8", "lsfe"}, {}},
1787+
{AArch64::ARMV9_6A, {"lsfe", "nofp"}, {}, {"fp-armv8", "lsfe"}},
1788+
1789+
// fp -> fprcvt
1790+
{AArch64::ARMV9_6A, {"nofp", "fprcvt"}, {"fp-armv8", "fprcvt"}, {}},
1791+
{AArch64::ARMV9_6A, {"fprcvt", "nofp"}, {}, {"fp-armv8", "fprcvt"}},
1792+
1793+
// simd -> {aes, sha2, sha3, sm4, f8f16mm, f8f32mm}
17861794
{AArch64::ARMV8A, {"nosimd", "aes"}, {"neon", "aes"}, {}},
17871795
{AArch64::ARMV8A, {"aes", "nosimd"}, {}, {"neon", "aes"}},
17881796
{AArch64::ARMV8A, {"nosimd", "sha2"}, {"neon", "sha2"}, {}},
@@ -1791,6 +1799,10 @@ AArch64ExtensionDependenciesBaseArchTestParams
17911799
{AArch64::ARMV8A, {"sha3", "nosimd"}, {}, {"neon", "sha3"}},
17921800
{AArch64::ARMV8A, {"nosimd", "sm4"}, {"neon", "sm4"}, {}},
17931801
{AArch64::ARMV8A, {"sm4", "nosimd"}, {}, {"neon", "sm4"}},
1802+
{AArch64::ARMV9_6A, {"nosimd", "f8f16mm"}, {"neon", "f8f16mm"}, {}},
1803+
{AArch64::ARMV9_6A, {"f8f16mm", "nosimd"}, {}, {"neon", "f8f16mm"}},
1804+
{AArch64::ARMV9_6A, {"nosimd", "f8f32mm"}, {"neon", "f8f32mm"}, {}},
1805+
{AArch64::ARMV9_6A, {"f8f32mm", "nosimd"}, {}, {"neon", "f8f32mm"}},
17941806

17951807
// simd -> {rdm, dotprod, fcma}
17961808
{AArch64::ARMV8A, {"nosimd", "rdm"}, {"neon", "rdm"}, {}},
@@ -1810,13 +1822,21 @@ AArch64ExtensionDependenciesBaseArchTestParams
18101822
{AArch64::ARMV8A, {"nobf16", "sme"}, {"bf16", "sme"}, {}},
18111823
{AArch64::ARMV8A, {"sme", "nobf16"}, {}, {"bf16", "sme"}},
18121824

1813-
// sve -> {sve2, f32mm, f64mm}
1825+
// sve -> {sve2, f32mm, f64mm, sve-f16f32mm}
18141826
{AArch64::ARMV8A, {"nosve", "sve2"}, {"sve", "sve2"}, {}},
18151827
{AArch64::ARMV8A, {"sve2", "nosve"}, {}, {"sve", "sve2"}},
18161828
{AArch64::ARMV8A, {"nosve", "f32mm"}, {"sve", "f32mm"}, {}},
18171829
{AArch64::ARMV8A, {"f32mm", "nosve"}, {}, {"sve", "f32mm"}},
18181830
{AArch64::ARMV8A, {"nosve", "f64mm"}, {"sve", "f64mm"}, {}},
18191831
{AArch64::ARMV8A, {"f64mm", "nosve"}, {}, {"sve", "f64mm"}},
1832+
{AArch64::ARMV9_6A,
1833+
{"nosve", "sve-f16f32mm"},
1834+
{"sve", "sve-f16f32mm"},
1835+
{}},
1836+
{AArch64::ARMV9_6A,
1837+
{"sve-f16f32mm", "nosve"},
1838+
{},
1839+
{"sve", "sve-f16f32mm"}},
18201840

18211841
// sve2 -> {sve2p1, sve2-bitperm, sve2-sha3, sve2-sm4}
18221842
{AArch64::ARMV8A, {"nosve2", "sve2p1"}, {"sve2", "sve2p1"}, {}},
@@ -1861,7 +1881,7 @@ AArch64ExtensionDependenciesBaseArchTestParams
18611881
{AArch64::ARMV8A, {"sme-fa64", "nosme"}, {}, {"sme", "sme-fa64"}},
18621882

18631883
// sme2 -> {sme2p1, ssve-fp8fma, ssve-fp8dot2, ssve-fp8dot4, sme-f8f16,
1864-
// sme-f8f32, sme-b16b16}
1884+
// sme-f8f32, sme-b16b16, ssve-aes}
18651885
{AArch64::ARMV8A, {"nosme2", "sme2p1"}, {"sme2", "sme2p1"}, {}},
18661886
{AArch64::ARMV8A, {"sme2p1", "nosme2"}, {}, {"sme2", "sme2p1"}},
18671887
{AArch64::ARMV8A,
@@ -1894,16 +1914,22 @@ AArch64ExtensionDependenciesBaseArchTestParams
18941914
{AArch64::ARMV8A, {"sme-f8f32", "nosme2"}, {}, {"sme2", "sme-f8f32"}},
18951915
{AArch64::ARMV8A, {"nosme2", "sme-b16b16"}, {"sme2", "sme-b16b16"}, {}},
18961916
{AArch64::ARMV8A, {"sme-b16b16", "nosme2"}, {}, {"sme2", "sme-b16b16"}},
1917+
{AArch64::ARMV9_6A, {"nosme2", "ssve-aes"}, {"sme2", "ssve-aes"}, {}},
1918+
{AArch64::ARMV9_6A, {"ssve-aes", "nosme2"}, {}, {"ssve-aes", "sme2"}},
18971919

18981920
// sme2p1 -> {sme2p2}
18991921
{AArch64::ARMV9_6A, {"nosme2p1", "sme2p2"}, {"sme2p2", "sme2p1"}, {}},
19001922
{AArch64::ARMV9_6A, {"sme2p2", "nosme2p1"}, {}, {"sme2p1", "sme2p2"}},
19011923

1902-
// fp8 -> {sme-f8f16, sme-f8f32}
1924+
// fp8 -> {sme-f8f16, sme-f8f32, f8f16mm, f8f32mm}
19031925
{AArch64::ARMV8A, {"nofp8", "sme-f8f16"}, {"fp8", "sme-f8f16"}, {}},
19041926
{AArch64::ARMV8A, {"sme-f8f16", "nofp8"}, {}, {"fp8", "sme-f8f16"}},
19051927
{AArch64::ARMV8A, {"nofp8", "sme-f8f32"}, {"fp8", "sme-f8f32"}, {}},
19061928
{AArch64::ARMV8A, {"sme-f8f32", "nofp8"}, {}, {"fp8", "sme-f8f32"}},
1929+
{AArch64::ARMV9_6A, {"nofp8", "f8f16mm"}, {"fp8", "f8f16mm"}, {}},
1930+
{AArch64::ARMV9_6A, {"f8f16mm", "nofp8"}, {}, {"fp8", "f8f16mm"}},
1931+
{AArch64::ARMV9_6A, {"nofp8", "f8f32mm"}, {"fp8", "f8f32mm"}, {}},
1932+
{AArch64::ARMV9_6A, {"f8f32mm", "nofp8"}, {}, {"fp8", "f8f32mm"}},
19071933

19081934
// lse -> lse128
19091935
{AArch64::ARMV8A, {"nolse", "lse128"}, {"lse", "lse128"}, {}},
@@ -1926,6 +1952,16 @@ AArch64ExtensionDependenciesBaseArchTestParams
19261952
// rcpc -> rcpc3
19271953
{AArch64::ARMV8A, {"norcpc", "rcpc3"}, {"rcpc", "rcpc3"}, {}},
19281954
{AArch64::ARMV8A, {"rcpc3", "norcpc"}, {}, {"rcpc", "rcpc3"}},
1955+
1956+
// sve2-aes -> ssve-aes
1957+
{AArch64::ARMV9_6A,
1958+
{"nosve2-aes", "ssve-aes"},
1959+
{"sve2-aes", "ssve-aes"},
1960+
{}},
1961+
{AArch64::ARMV9_6A,
1962+
{"ssve-aes", "nosve2-aes"},
1963+
{},
1964+
{"ssve-aes", "sve2-aes"}},
19291965
};
19301966

19311967
INSTANTIATE_TEST_SUITE_P(

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