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add cir tests, cast signed amts to unsigned
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+48
-3
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2 files changed

+48
-3
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clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include "mlir/IR/ValueRange.h"
1717
#include "clang/Basic/Builtins.h"
1818
#include "clang/Basic/TargetBuiltins.h"
19+
#include "clang/CIR/Dialect/IR/CIRTypes.h"
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#include "clang/CIR/MissingFeatures.h"
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2122
using namespace clang;
@@ -100,10 +101,17 @@ static mlir::Value emitX86FunnelShift(CIRGenFunction &cgf, const CallExpr *e,
100101
// Funnel shifts amounts are treated as modulo and types are all power-of-2
101102
// so we only care about the lowest log2 bits anyway.
102103
if (amt.getType() != ty) {
103-
amt = cgf.getBuilder().createIntCast(
104-
amt, mlir::cast<cir::VectorType>(ty).getElementType());
104+
auto vecTy = mlir::cast<cir::VectorType>(ty);
105+
106+
auto numElems = vecTy.getSize();
107+
cir::IntType vecElemType = mlir::cast<cir::IntType>(vecTy.getElementType());
108+
auto signlessType =
109+
cir::IntType::get(&cgf.getMLIRContext(), vecElemType.getWidth(), false);
110+
amt = cgf.getBuilder().createIntCast(amt, signlessType);
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105112
amt = cir::VecSplatOp::create(cgf.getBuilder(), cgf.getLoc(e->getExprLoc()),
106-
ty, amt);
113+
cir::VectorType::get(signlessType, numElems),
114+
amt);
107115
}
108116

109117
const std::string intrinsicName = isRight ? "fshr" : "fshl";

clang/test/CIR/CodeGen/X86/xop-builtin.c renamed to clang/test/CIR/CodeGen/X86/xop-builtins.c

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,4 +39,41 @@ __m128i test_mm_roti_epi8(__m128i a) {
3939
// OGCG: %[[CASTED_VAR:.*]] = bitcast <2 x i64> {{%.*}} to <16 x i8>
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// OGCG: {{%.*}} = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %[[CASTED_VAR]], <16 x i8> %[[CASTED_VAR]], <16 x i8> splat (i8 1))
4141
return _mm_roti_epi8(a, 1);
42+
}
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44+
__m128i test_mm_roti_epi16(__m128i a) {
45+
// CIR-LABEL: test_mm_roti_epi16
46+
// CIR: {{%.*}} = cir.cast integral {{%.*}} : !{{[us]}}8i -> !u16i
47+
// CIR: {{%.*}} = cir.vec.splat {{%.*}} : !{{[us]}}16i, !cir.vector<8 x !{{[us]}}16i>
48+
// CIR: {{%.*}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<8 x !{{[su]}}16i>, !cir.vector<8 x !{{[su]}}16i>, !cir.vector<8 x !{{[su]}}16i>) -> !cir.vector<8 x !{{[su]}}16i>
49+
// LLVM-LABEL: test_mm_roti_epi16
50+
// LLVM: %[[CASTED_VAR:.*]] = bitcast <2 x i64> {{%.*}} to <8 x i16>
51+
// LLVM: {{%.*}} = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %[[CASTED_VAR]], <8 x i16> %[[CASTED_VAR]], <8 x i16> splat (i16 50))
52+
// OGCG-LABEL: test_mm_roti_epi16
53+
// OGCG: %[[CASTED_VAR:.*]] = bitcast <2 x i64> {{%.*}} to <8 x i16>
54+
// OGCG: {{%.*}} = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %[[CASTED_VAR]], <8 x i16> %[[CASTED_VAR]], <8 x i16> splat (i16 50))
55+
return _mm_roti_epi16(a, 50);
56+
}
57+
58+
//NOTE: This only works as I expect for CIR but not for LLVMIR
59+
__m128i test_mm_roti_epi32(__m128i a) {
60+
// CIR-LABEL: test_mm_roti_epi32
61+
// CIR: {{%.*}} = cir.cast integral {{%.*}} : !{{[us]}}8i -> !u32i
62+
// CIR: {{%.*}} = cir.vec.splat {{%.*}} : !{{[us]}}32i, !cir.vector<4 x !{{[us]}}32i>
63+
// CIR: {{%.*}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<4 x !{{[su]}}32i>, !cir.vector<4 x !{{[su]}}32i>, !cir.vector<4 x !{{[su]}}32i>) -> !cir.vector<4 x !{{[su]}}32i>
64+
return _mm_roti_epi32(a, -30);
65+
}
66+
67+
__m128i test_mm_roti_epi64(__m128i a) {
68+
// CIR-LABEL: test_mm_roti_epi64
69+
// CIR: {{%.*}} = cir.cast integral {{%.*}} : !{{[us]}}8i -> !u64i
70+
// CIR: {{%.*}} = cir.vec.splat {{%.*}} : !{{.}}64i, !cir.vector<2 x !{{[us]}}64i>
71+
// CIR: {{%.*}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<2 x !{{[su]}}64i>, !cir.vector<2 x !{{[su]}}64i>, !cir.vector<2 x !u64i>) -> !cir.vector<2 x !{{[su]}}64i>
72+
// LLVM-LABEL: test_mm_roti_epi64
73+
// LLVM: %[[VAR:.*]] = load <2 x i64>, ptr {{%.*}}, align 16
74+
// LLVM: {{%.*}} = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %[[VAR]], <2 x i64> %[[VAR]], <2 x i64> splat (i64 100))
75+
// OGCG-LABEL: test_mm_roti_epi64
76+
// OGCG: %[[VAR:.*]] = load <2 x i64>, ptr {{%.*}}, align 16
77+
// OGCG: {{%.*}} = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %[[VAR]], <2 x i64> %[[VAR]], <2 x i64> splat (i64 100))
78+
return _mm_roti_epi64(a, 100);
4279
}

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