@@ -39,4 +39,41 @@ __m128i test_mm_roti_epi8(__m128i a) {
3939 // OGCG: %[[CASTED_VAR:.*]] = bitcast <2 x i64> {{%.*}} to <16 x i8>
4040 // OGCG: {{%.*}} = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %[[CASTED_VAR]], <16 x i8> %[[CASTED_VAR]], <16 x i8> splat (i8 1))
4141 return _mm_roti_epi8 (a , 1 );
42+ }
43+
44+ __m128i test_mm_roti_epi16 (__m128i a ) {
45+ // CIR-LABEL: test_mm_roti_epi16
46+ // CIR: {{%.*}} = cir.cast integral {{%.*}} : !{{[us]}}8i -> !u16i
47+ // CIR: {{%.*}} = cir.vec.splat {{%.*}} : !{{[us]}}16i, !cir.vector<8 x !{{[us]}}16i>
48+ // CIR: {{%.*}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<8 x !{{[su]}}16i>, !cir.vector<8 x !{{[su]}}16i>, !cir.vector<8 x !{{[su]}}16i>) -> !cir.vector<8 x !{{[su]}}16i>
49+ // LLVM-LABEL: test_mm_roti_epi16
50+ // LLVM: %[[CASTED_VAR:.*]] = bitcast <2 x i64> {{%.*}} to <8 x i16>
51+ // LLVM: {{%.*}} = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %[[CASTED_VAR]], <8 x i16> %[[CASTED_VAR]], <8 x i16> splat (i16 50))
52+ // OGCG-LABEL: test_mm_roti_epi16
53+ // OGCG: %[[CASTED_VAR:.*]] = bitcast <2 x i64> {{%.*}} to <8 x i16>
54+ // OGCG: {{%.*}} = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %[[CASTED_VAR]], <8 x i16> %[[CASTED_VAR]], <8 x i16> splat (i16 50))
55+ return _mm_roti_epi16 (a , 50 );
56+ }
57+
58+ //NOTE: This only works as I expect for CIR but not for LLVMIR
59+ __m128i test_mm_roti_epi32 (__m128i a ) {
60+ // CIR-LABEL: test_mm_roti_epi32
61+ // CIR: {{%.*}} = cir.cast integral {{%.*}} : !{{[us]}}8i -> !u32i
62+ // CIR: {{%.*}} = cir.vec.splat {{%.*}} : !{{[us]}}32i, !cir.vector<4 x !{{[us]}}32i>
63+ // CIR: {{%.*}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<4 x !{{[su]}}32i>, !cir.vector<4 x !{{[su]}}32i>, !cir.vector<4 x !{{[su]}}32i>) -> !cir.vector<4 x !{{[su]}}32i>
64+ return _mm_roti_epi32 (a , -30 );
65+ }
66+
67+ __m128i test_mm_roti_epi64 (__m128i a ) {
68+ // CIR-LABEL: test_mm_roti_epi64
69+ // CIR: {{%.*}} = cir.cast integral {{%.*}} : !{{[us]}}8i -> !u64i
70+ // CIR: {{%.*}} = cir.vec.splat {{%.*}} : !{{.}}64i, !cir.vector<2 x !{{[us]}}64i>
71+ // CIR: {{%.*}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<2 x !{{[su]}}64i>, !cir.vector<2 x !{{[su]}}64i>, !cir.vector<2 x !u64i>) -> !cir.vector<2 x !{{[su]}}64i>
72+ // LLVM-LABEL: test_mm_roti_epi64
73+ // LLVM: %[[VAR:.*]] = load <2 x i64>, ptr {{%.*}}, align 16
74+ // LLVM: {{%.*}} = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %[[VAR]], <2 x i64> %[[VAR]], <2 x i64> splat (i64 100))
75+ // OGCG-LABEL: test_mm_roti_epi64
76+ // OGCG: %[[VAR:.*]] = load <2 x i64>, ptr {{%.*}}, align 16
77+ // OGCG: {{%.*}} = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %[[VAR]], <2 x i64> %[[VAR]], <2 x i64> splat (i64 100))
78+ return _mm_roti_epi64 (a , 100 );
4279 }
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