address comments

Author: chencha3

mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h

@@ -17,9 +17,9 @@ namespace xegpu {
 /// Options to control the XeGPU unrolling. Its main purpose is to
 /// provide a way to customize the native shape of the operation.
 struct UnrollOptions {
-  using FilterConstraintFnType = std::function<LogicalResult(Operation *op)>;
   /// Callback function that indicates whether vector unrolling should be
   /// attempted on the operation.
+  using FilterConstraintFnType = std::function<LogicalResult(Operation *op)>;
   FilterConstraintFnType filterConstraint = nullptr;
   UnrollOptions &setFilterConstraint(FilterConstraintFnType constraint) {
     filterConstraint = std::move(constraint);

mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp

@@ -136,9 +136,9 @@ struct UnrollPattern : public OpRewritePattern<SourceOp> {
   }
 
 private:
-  const char *const packAttrName = "__xetile_blocking_pack__";
-  const char *const unpackAttrName = "__xetile_blocking_unpack__";
-  const char *const blockAttrName = "__xetile_blocking_inner_block__";
+  const char *const packAttrName = "__xegpu_blocking_pack__";
+  const char *const unpackAttrName = "__xegpu_blocking_unpack__";
+  const char *const blockAttrName = "__xegpu_blocking_tile_shape__";
 
   xegpu::UnrollOptions options;
 };

mlir/test/Dialect/XeGPU/xegpu-unroll-patterns.mlir

@@ -9,7 +9,7 @@ gpu.module @test {
   // CHECK-SAME: !xegpu.tensor_desc<8x16xf32>, !xegpu.tensor_desc<8x16xf32>,
   // CHECK-SAME: !xegpu.tensor_desc<8x16xf32>, !xegpu.tensor_desc<8x16xf32>,
   // CHECK-SAME: !xegpu.tensor_desc<8x16xf32>, !xegpu.tensor_desc<8x16xf32>
-  // CHECK-SAME: to !xegpu.tensor_desc<24x32xf32, #xegpu.layout<inst_data = [8, 16]>> {__xetile_blocking_inner_block__ = array<i64: 8, 16>, __xetile_blocking_unpack__}
+  // CHECK-SAME: to !xegpu.tensor_desc<24x32xf32, #xegpu.layout<inst_data = [8, 16]>> {__xegpu_blocking_tile_shape__ = array<i64: 8, 16>, __xegpu_blocking_unpack__}
   gpu.func @test_create_nd_tdesc(%src: memref<24x32xf32>) -> !xegpu.tensor_desc<24x32xf32, #xegpu.layout<inst_data = [8, 16]>> {
     %tdesc = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> -> !xegpu.tensor_desc<24x32xf32, #xegpu.layout<inst_data = [8, 16]>>
     gpu.return %tdesc : !xegpu.tensor_desc<24x32xf32, #xegpu.layout<inst_data = [8, 16]>>
@@ -22,7 +22,7 @@ gpu.module @test {
   // CHECK-COUNT-2: [[tdesc:%.+]] = xegpu.create_nd_tdesc [[arg0]][{{.*}}] : memref<64xf32> -> !xegpu.tensor_desc<16xf32>
   // CHECK: [[cast:%.+]] = builtin.unrealized_conversion_cast
   // CHECK-SAME: !xegpu.tensor_desc<16xf32>, !xegpu.tensor_desc<16xf32>
-  // CHECK-SAME: to !xegpu.tensor_desc<32xf32, #xegpu.layout<inst_data = [16]>> {__xetile_blocking_inner_block__ = array<i64: 16>, __xetile_blocking_unpack__}
+  // CHECK-SAME: to !xegpu.tensor_desc<32xf32, #xegpu.layout<inst_data = [16]>> {__xegpu_blocking_tile_shape__ = array<i64: 16>, __xegpu_blocking_unpack__}
   gpu.func @test_create_nd_tdesc_1d(%src: memref<64xf32>) -> !xegpu.tensor_desc<32xf32, #xegpu.layout<inst_data = [16]>> {
     %tdesc = xegpu.create_nd_tdesc %src[0] : memref<64xf32> -> !xegpu.tensor_desc<32xf32, #xegpu.layout<inst_data = [16]>>
     gpu.return %tdesc : !xegpu.tensor_desc<32xf32, #xegpu.layout<inst_data = [16]>>