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[MC] Reorder TARGETInstrTable to shrink MCInstrDesc::ImplicitOffset
Put ImplicitOps[] before OperandInfo[] in the generated TARGETInstrTable. This means that offsets to entries into the (small) ImplicitOps table do not need to skip over the (large) OperandInfo table. This allows shrinking ImplicitOffset from 32 bits to 16 bits (effectively reverting #138127) which will allow expanding Opcode instead without increasing the size of MCInstrDesc.
1 parent 07bafab commit 972235e

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4 files changed

+38
-24
lines changed

4 files changed

+38
-24
lines changed

‎llvm/include/llvm/MC/MCInstrDesc.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -211,7 +211,7 @@ class MCInstrDesc {
211211
unsigned char NumImplicitUses; // Num of regs implicitly used
212212
unsigned char NumImplicitDefs; // Num of regs implicitly defined
213213
unsigned short OpInfoOffset; // Offset to info about operands
214-
unsigned int ImplicitOffset; // Offset to start of implicit op list
214+
unsigned short ImplicitOffset; // Offset to start of implicit op list
215215
uint64_t Flags; // Flags identifying machine instr class
216216
uint64_t TSFlags; // Target Specific Flag values
217217

‎llvm/test/TableGen/RegClassByHwMode.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ include "llvm/Target/Target.td"
2424
// INSTRINFO-NEXT: } // namespace llvm::MyTarget
2525

2626

27-
// INSTRINFO: { [[LOAD_STACK_GUARD_OPCODE]], 1, 1, 0, 0, 0, 0, [[LOAD_STACK_GUARD_OP_INDEX:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
27+
// INSTRINFO: { [[LOAD_STACK_GUARD_OPCODE]], 1, 1, 0, 0, 0, 0, MyTargetOpInfoBase + [[LOAD_STACK_GUARD_OP_INDEX:[0-9]+]], 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
2828

2929
// INSTRINFO: /* [[LOAD_STACK_GUARD_OP_INDEX]] */ { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },
3030
// INSTRINFO: { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },

‎llvm/test/TableGen/target-specialized-pseudos.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -22,13 +22,13 @@
2222

2323
// CHECK: extern const MyTargetInstrTable MyTargetDescs = {
2424
// CHECK-NEXT: {
25-
// CHECK-NEXT: { [[MY_MOV_OPCODE]], 2, 1, 2, 0, 0, 0, {{[0-9]+}}, MyTargetImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MY_MOV
26-
// CHECK-NEXT: { [[G_UBFX_OPCODE]], 4, 1, 0, 0, 0, 0, {{[0-9]+}}, MyTargetImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
25+
// CHECK-NEXT: { [[MY_MOV_OPCODE]], 2, 1, 2, 0, 0, 0, MyTargetOpInfoBase + {{[0-9]+}}, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MY_MOV
26+
// CHECK-NEXT: { [[G_UBFX_OPCODE]], 4, 1, 0, 0, 0, 0, MyTargetOpInfoBase + {{[0-9]+}}, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
2727

28-
// ALLCASES: { [[PATCHABLE_TYPED_EVENT_CALL_OPCODE]], 3, 0, 0, 0, 0, 0, [[PATCHABLE_TYPED_EVENT_CALL_OP_ENTRY:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
29-
// ALLCASES: { [[PATCHABLE_EVENT_CALL_OPCODE]], 2, 0, 0, 0, 0, 0, [[PATCHABLE_EVENT_CALL_OP_ENTRY:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
30-
// ALLCASES: { [[PREALLOCATED_ARG_OPCODE]], 3, 1, 0, 0, 0, 0, [[PREALLOCATED_ARG_OP_ENTRY:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
31-
// ALLCASES: { [[LOAD_STACK_GUARD_OPCODE]], 1, 1, 0, 0, 0, 0, [[LOAD_STACK_GUARD_OP_ENTRY:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
28+
// ALLCASES: { [[PATCHABLE_TYPED_EVENT_CALL_OPCODE]], 3, 0, 0, 0, 0, 0, MyTargetOpInfoBase + [[PATCHABLE_TYPED_EVENT_CALL_OP_ENTRY:[0-9]+]], 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
29+
// ALLCASES: { [[PATCHABLE_EVENT_CALL_OPCODE]], 2, 0, 0, 0, 0, 0, MyTargetOpInfoBase + [[PATCHABLE_EVENT_CALL_OP_ENTRY:[0-9]+]], 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
30+
// ALLCASES: { [[PREALLOCATED_ARG_OPCODE]], 3, 1, 0, 0, 0, 0, MyTargetOpInfoBase + [[PREALLOCATED_ARG_OP_ENTRY:[0-9]+]], 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
31+
// ALLCASES: { [[LOAD_STACK_GUARD_OPCODE]], 1, 1, 0, 0, 0, 0, MyTargetOpInfoBase + [[LOAD_STACK_GUARD_OP_ENTRY:[0-9]+]], 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
3232

3333
// CHECK: /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3434

‎llvm/utils/TableGen/InstrInfoEmitter.cpp‎

Lines changed: 30 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -959,13 +959,19 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
959959

960960
OS << "struct " << TargetName << "InstrTable {\n";
961961
OS << " MCInstrDesc Insts[" << NumberedInstructions.size() << "];\n";
962+
OS << " static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "
963+
"\"Unwanted padding between Insts and ImplicitOps\");\n";
964+
OS << " MCPhysReg ImplicitOps[" << std::max(ImplicitListSize, 1U)
965+
<< "];\n";
966+
// Emit enough padding to make ImplicitOps plus Padding add up to the size
967+
// of a whole number of MCOperandInfo structs. This allows us to index into
968+
// the OperandInfo array starting from the end of the Insts array, by
969+
// biasing the indices by the OpInfoBase value calculated below.
970+
OS << " char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % "
971+
"sizeof(MCOperandInfo)];\n";
962972
OS << " static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "
963973
"\"Unwanted padding between Insts and OperandInfo\");\n";
964974
OS << " MCOperandInfo OperandInfo[" << OperandInfoSize << "];\n";
965-
OS << " static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "
966-
"\"Unwanted padding between OperandInfo and ImplicitOps\");\n";
967-
OS << " MCPhysReg ImplicitOps[" << std::max(ImplicitListSize, 1U)
968-
<< "];\n";
969975
OS << "};";
970976
}
971977

@@ -991,9 +997,12 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
991997

992998
// Emit all of the MCInstrDesc records in reverse ENUM ordering.
993999
Timer.startTimer("Emit InstrDesc records");
994-
OS << "static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);\n";
995-
OS << "static constexpr unsigned " << TargetName << "ImpOpBase = sizeof "
996-
<< TargetName << "InstrTable::OperandInfo / (sizeof(MCPhysReg));\n\n";
1000+
OS << "static_assert((sizeof " << TargetName
1001+
<< "InstrTable::ImplicitOps + sizeof " << TargetName
1002+
<< "InstrTable::Padding) % sizeof(MCOperandInfo) == 0);\n";
1003+
OS << "static constexpr unsigned " << TargetName << "OpInfoBase = (sizeof "
1004+
<< TargetName << "InstrTable::ImplicitOps + sizeof " << TargetName
1005+
<< "InstrTable::Padding) / sizeof(MCOperandInfo);\n\n";
9971006

9981007
OS << "extern const " << TargetName << "InstrTable " << TargetName
9991008
<< "Descs = {\n {\n";
@@ -1013,12 +1022,6 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
10131022

10141023
OS << " }, {\n";
10151024

1016-
// Emit all of the operand info records.
1017-
Timer.startTimer("Emit operand info");
1018-
EmitOperandInfo(OS, OperandInfoList);
1019-
1020-
OS << " }, {\n";
1021-
10221025
// Emit all of the instruction's implicit uses and defs.
10231026
Timer.startTimer("Emit uses/defs");
10241027
for (auto &List : ImplicitLists) {
@@ -1028,6 +1031,17 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
10281031
OS << '\n';
10291032
}
10301033

1034+
OS << " }, {\n";
1035+
1036+
// Emit the padding.
1037+
OS << " 0\n";
1038+
1039+
OS << " }, {\n";
1040+
1041+
// Emit all of the operand info records.
1042+
Timer.startTimer("Emit operand info");
1043+
EmitOperandInfo(OS, OperandInfoList);
1044+
10311045
OS << " }\n};\n\n";
10321046

10331047
// Emit the array of instruction names.
@@ -1291,11 +1305,11 @@ void InstrInfoEmitter::emitRecord(
12911305

12921306
// Emit the operand info offset.
12931307
OperandInfoTy OperandInfo = GetOperandInfo(Inst);
1294-
OS << OperandInfoMap.find(OperandInfo)->second << ",\t";
1308+
OS << Target.getName() << "OpInfoBase + "
1309+
<< OperandInfoMap.find(OperandInfo)->second << ",\t";
12951310

12961311
// Emit implicit operand base.
1297-
OS << Target.getName() << "ImpOpBase + " << EmittedLists[ImplicitOps]
1298-
<< ",\t0";
1312+
OS << EmittedLists[ImplicitOps] << ",\t0";
12991313

13001314
// Emit all of the target independent flags...
13011315
if (Inst.isPreISelOpcode)

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