Update changes due to scheduling.

Author: lei137

llvm/test/CodeGen/PowerPC/p10-spill-crun.ll

@@ -234,8 +234,8 @@ define dso_local void @P10_Spill_CR_UN(ptr %arg, ptr %arg1, i32 %arg2) local_unn
 ; CHECK-BE-NEXT:  # %bb.4: # %bb37
 ; CHECK-BE-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
 ; CHECK-BE-NEXT:  .LBB0_5: # %bb42
-; CHECK-BE-NEXT:    addi r3, r3, global_1@toc@l
 ; CHECK-BE-NEXT:    li r4, 0
+; CHECK-BE-NEXT:    addi r3, r3, global_1@toc@l
 ; CHECK-BE-NEXT:    cmpwi r28, 0
 ; CHECK-BE-NEXT:    isel r3, r3, r4, 4*cr2+gt
 ; CHECK-BE-NEXT:    crnot 4*cr2+lt, eq

llvm/test/CodeGen/PowerPC/vector-reduce-add.ll

@@ -1085,14 +1085,14 @@ define dso_local signext i32 @v16i8tov16i32_sign(<16 x i8> %a) local_unnamed_add
 ; PWR10BE-NEXT:    addis r3, r2, .LCPI17_2@toc@ha
 ; PWR10BE-NEXT:    vperm v3, v2, v2, v3
 ; PWR10BE-NEXT:    addi r3, r3, .LCPI17_2@toc@l
-; PWR10BE-NEXT:    vextsb2w v3, v3
 ; PWR10BE-NEXT:    lxv v5, 0(r3)
 ; PWR10BE-NEXT:    addis r3, r2, .LCPI17_3@toc@ha
+; PWR10BE-NEXT:    vextsb2w v3, v3
 ; PWR10BE-NEXT:    vperm v4, v2, v2, v4
 ; PWR10BE-NEXT:    addi r3, r3, .LCPI17_3@toc@l
-; PWR10BE-NEXT:    vextsb2w v4, v4
 ; PWR10BE-NEXT:    lxv v0, 0(r3)
 ; PWR10BE-NEXT:    li r3, 0
+; PWR10BE-NEXT:    vextsb2w v4, v4
 ; PWR10BE-NEXT:    vperm v5, v2, v2, v5
 ; PWR10BE-NEXT:    vadduwm v3, v4, v3
 ; PWR10BE-NEXT:    vextsb2w v5, v5
@@ -1212,9 +1212,9 @@ define dso_local zeroext i32 @v16i8tov16i32_zero(<16 x i8> %a) local_unnamed_add
 ; PWR10BE-NEXT:    addis r3, r2, .LCPI18_3@toc@ha
 ; PWR10BE-NEXT:    vperm v5, v4, v2, v5
 ; PWR10BE-NEXT:    addi r3, r3, .LCPI18_3@toc@l
-; PWR10BE-NEXT:    vadduwm v3, v5, v3
 ; PWR10BE-NEXT:    lxv v1, 0(r3)
 ; PWR10BE-NEXT:    li r3, 0
+; PWR10BE-NEXT:    vadduwm v3, v5, v3
 ; PWR10BE-NEXT:    vperm v0, v4, v2, v0
 ; PWR10BE-NEXT:    vperm v2, v4, v2, v1
 ; PWR10BE-NEXT:    vadduwm v2, v2, v0
@@ -1574,36 +1574,36 @@ define dso_local i64 @v16i8tov16i64_sign(<16 x i8> %a) local_unnamed_addr #0 {
 ; PWR10BE-NEXT:    addis r3, r2, .LCPI23_2@toc@ha
 ; PWR10BE-NEXT:    vperm v3, v2, v2, v3
 ; PWR10BE-NEXT:    addi r3, r3, .LCPI23_2@toc@l
-; PWR10BE-NEXT:    vextsb2d v3, v3
 ; PWR10BE-NEXT:    lxv v5, 0(r3)
 ; PWR10BE-NEXT:    addis r3, r2, .LCPI23_3@toc@ha
+; PWR10BE-NEXT:    vextsb2d v3, v3
 ; PWR10BE-NEXT:    vperm v4, v2, v2, v4
 ; PWR10BE-NEXT:    addi r3, r3, .LCPI23_3@toc@l
-; PWR10BE-NEXT:    vextsb2d v4, v4
 ; PWR10BE-NEXT:    lxv v0, 0(r3)
 ; PWR10BE-NEXT:    addis r3, r2, .LCPI23_4@toc@ha
+; PWR10BE-NEXT:    vextsb2d v4, v4
 ; PWR10BE-NEXT:    vperm v5, v2, v2, v5
 ; PWR10BE-NEXT:    addi r3, r3, .LCPI23_4@toc@l
-; PWR10BE-NEXT:    vextsb2d v5, v5
 ; PWR10BE-NEXT:    lxv v1, 0(r3)
 ; PWR10BE-NEXT:    addis r3, r2, .LCPI23_5@toc@ha
+; PWR10BE-NEXT:    vextsb2d v5, v5
 ; PWR10BE-NEXT:    vperm v0, v2, v2, v0
 ; PWR10BE-NEXT:    addi r3, r3, .LCPI23_5@toc@l
-; PWR10BE-NEXT:    vextsb2d v0, v0
 ; PWR10BE-NEXT:    lxv v6, 0(r3)
 ; PWR10BE-NEXT:    addis r3, r2, .LCPI23_6@toc@ha
+; PWR10BE-NEXT:    vextsb2d v0, v0
 ; PWR10BE-NEXT:    vperm v1, v2, v2, v1
+; PWR10BE-NEXT:    addi r3, r3, .LCPI23_6@toc@l
 ; PWR10BE-NEXT:    vaddudm v5, v0, v5
 ; PWR10BE-NEXT:    vaddudm v3, v4, v3
 ; PWR10BE-NEXT:    vaddudm v3, v3, v5
-; PWR10BE-NEXT:    addi r3, r3, .LCPI23_6@toc@l
-; PWR10BE-NEXT:    vextsb2d v1, v1
 ; PWR10BE-NEXT:    lxv v7, 0(r3)
 ; PWR10BE-NEXT:    addis r3, r2, .LCPI23_7@toc@ha
+; PWR10BE-NEXT:    vextsb2d v1, v1
 ; PWR10BE-NEXT:    vperm v6, v2, v2, v6
 ; PWR10BE-NEXT:    addi r3, r3, .LCPI23_7@toc@l
-; PWR10BE-NEXT:    vextsb2d v6, v6
 ; PWR10BE-NEXT:    lxv v8, 0(r3)
+; PWR10BE-NEXT:    vextsb2d v6, v6
 ; PWR10BE-NEXT:    vperm v7, v2, v2, v7
 ; PWR10BE-NEXT:    vextsb2d v7, v7
 ; PWR10BE-NEXT:    vperm v2, v2, v2, v8