Merge branch 'main' into x86-concat-v2f64-shuffles

Author: RKSimon

clang/bindings/python/clang/cindex.py

@@ -2481,6 +2481,7 @@ def spelling(self):
     OBJCSEL = 29
     FLOAT128 = 30
     HALF = 31
+    FLOAT16 = 32
     IBM128 = 40
     COMPLEX = 100
     POINTER = 101

lldb/test/Shell/Settings/TestFrameFunctionInlined.test

@@ -1,7 +1,12 @@
 # Test the ${function.is-inlined} frame-format variable.
 
+# Windows' link.exe does not preserve DWARF information, and we cannot get
+# inlining information from PDB at this time, see:
+# https://github.com/llvm/llvm-project/issues/143104
+# REQUIRES: (system-windows && lld) || !system-windows
+
 # RUN: split-file %s %t
-# RUN: %clang_host -g -gdwarf %t/main.cpp -o %t.out
+# RUN: %clang_host -g -gdwarf %t/main.cpp -o %t.out %if system-windows %{-fuse-ld=lld%}
 # RUN: %lldb -x -b -s %t/commands.input %t.out -o exit 2>&1 \
 # RUN:       | FileCheck %s
 
@@ -28,7 +33,7 @@ run
 bt
 
 # CHECK:      (lldb) bt
-# CHECK:      frame 'inlined1() (Inlined)'
-# CHECK-NEXT: frame 'regular()'
-# CHECK-NEXT: frame 'inlined2() (Inlined)'
+# CHECK:      frame '{{.*}}inlined1({{.*}}) (Inlined)'
+# CHECK-NEXT: frame '{{.*}}regular({{.*}})'
+# CHECK-NEXT: frame '{{.*}}inlined2({{.*}}) (Inlined)'
 # CHECK-NEXT: frame 'main'

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

@@ -763,22 +763,25 @@ bool MIRParserImpl::setupRegisterInfo(const PerFunctionMIParsingState &PFS,
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
 
-  bool Error = false;
+  SmallVector<std::string> Errors;
+
   // Create VRegs
   auto populateVRegInfo = [&](const VRegInfo &Info, const Twine &Name) {
     Register Reg = Info.VReg;
     switch (Info.Kind) {
     case VRegInfo::UNKNOWN:
-      error(Twine("Cannot determine class/bank of virtual register ") +
-            Name + " in function '" + MF.getName() + "'");
-      Error = true;
+      Errors.push_back(
+          (Twine("Cannot determine class/bank of virtual register ") + Name +
+           " in function '" + MF.getName() + "'")
+              .str());
       break;
     case VRegInfo::NORMAL:
       if (!Info.D.RC->isAllocatable()) {
-        error(Twine("Cannot use non-allocatable class '") +
-              TRI->getRegClassName(Info.D.RC) + "' for virtual register " +
-              Name + " in function '" + MF.getName() + "'");
-        Error = true;
+        Errors.push_back((Twine("Cannot use non-allocatable class '") +
+                          TRI->getRegClassName(Info.D.RC) +
+                          "' for virtual register " + Name + " in function '" +
+                          MF.getName() + "'")
+                             .str());
         break;
       }
 
@@ -820,7 +823,14 @@ bool MIRParserImpl::setupRegisterInfo(const PerFunctionMIParsingState &PFS,
     }
   }
 
-  return Error;
+  if (Errors.empty())
+    return false;
+
+  // Report errors in a deterministic order.
+  sort(Errors);
+  for (auto &E : Errors)
+    error(E);
+  return true;
 }
 
 bool MIRParserImpl::initializeFrameInfo(PerFunctionMIParsingState &PFS,

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

@@ -6634,8 +6634,12 @@ SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
     InOp1 = GetWidenedVector(InOp1);
     InOp2 = GetWidenedVector(InOp2);
   } else {
-    InOp1 = DAG.WidenVector(InOp1, SDLoc(N));
-    InOp2 = DAG.WidenVector(InOp2, SDLoc(N));
+    SDValue Poison = DAG.getPOISON(WidenInVT);
+    SDValue ZeroIdx = DAG.getVectorIdxConstant(0, SDLoc(N));
+    InOp1 = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), WidenInVT, Poison,
+                        InOp1, ZeroIdx);
+    InOp2 = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), WidenInVT, Poison,
+                        InOp2, ZeroIdx);
   }
 
   // Assume that the input and output will be widen appropriately.  If not,

llvm/lib/Support/Unix/Threading.inc

@@ -318,6 +318,7 @@ static int computeHostNumHardwareThreads() {
     return CPU_COUNT(&mask);
 #elif defined(__linux__)
   cpu_set_t Set;
+  CPU_ZERO(&Set);
   if (sched_getaffinity(0, sizeof(Set), &Set) == 0)
     return CPU_COUNT(&Set);
 #endif

llvm/lib/Target/X86/X86TargetTransformInfo.cpp

@@ -5993,12 +5993,19 @@ InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
     // This is an imperfect hack to prevent constant hoisting of
     // compares that might be trying to check if a 64-bit value fits in
     // 32-bits. The backend can optimize these cases using a right shift by 32.
-    // Ideally we would check the compare predicate here. There also other
-    // similar immediates the backend can use shifts for.
+    // There are other predicates and immediates the backend can use shifts for.
     if (Idx == 1 && ImmBitWidth == 64) {
       uint64_t ImmVal = Imm.getZExtValue();
       if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff)
         return TTI::TCC_Free;
+
+      if (auto *Cmp = dyn_cast_or_null<CmpInst>(Inst)) {
+        if (Cmp->isEquality()) {
+          KnownBits Known = computeKnownBits(Cmp->getOperand(0), DL);
+          if (Known.countMinTrailingZeros() >= 32)
+            return TTI::TCC_Free;
+        }
+      }
     }
     ImmIdx = 1;
     break;

llvm/test/Analysis/BasicAA/captures.ll

@@ -40,3 +40,42 @@ define void @address_capture_and_full_capture() {
   load i32, ptr %a
   ret void
 }
+
+; CHECK-LABEL: address_capture_and_full_capture_commuted
+; CHECK: MayAlias:	i32* %a, i32* %p
+; CHECK: Both ModRef:  Ptr: i32* %a	<->  %p = call ptr @get_ptr()
+define void @address_capture_and_full_capture_commuted() {
+  %a = alloca i32
+  call void @capture(ptr %a)
+  call void @capture(ptr captures(address) %a)
+  %p = call ptr @get_ptr()
+  store i32 0, ptr %p
+  load i32, ptr %a
+  ret void
+}
+
+; CHECK-LABEL: read_only_capture_and_full_capture
+; CHECK: MayAlias:	i32* %a, i32* %p
+; CHECK: Both ModRef:  Ptr: i32* %a	<->  %p = call ptr @get_ptr()
+define void @read_only_capture_and_full_capture() {
+  %a = alloca i32
+  call void @capture(ptr captures(address, read_provenance) %a)
+  call void @capture(ptr %a)
+  %p = call ptr @get_ptr()
+  store i32 0, ptr %p
+  load i32, ptr %a
+  ret void
+}
+
+; CHECK-LABEL: read_only_capture_and_full_capture_commuted
+; CHECK: MayAlias:	i32* %a, i32* %p
+; CHECK: Both ModRef:  Ptr: i32* %a	<->  %p = call ptr @get_ptr()
+define void @read_only_capture_and_full_capture_commuted() {
+  %a = alloca i32
+  call void @capture(ptr %a)
+  call void @capture(ptr captures(address, read_provenance) %a)
+  %p = call ptr @get_ptr()
+  store i32 0, ptr %p
+  load i32, ptr %a
+  ret void
+}

llvm/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll

@@ -249,3 +249,19 @@ if.then:
 if.end:
   ret i32 1;
 }
+
+define <1 x i64> @test_zext_half(<1 x half> %v1) {
+; CHECK-LABEL: test_zext_half:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $h0 killed $h0 def $d0
+; CHECK-NEXT:    mov w8, #1 // =0x1
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    fcmgt v0.4s, v0.4s, #0.0
+; CHECK-NEXT:    xtn v0.4h, v0.4s
+; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT:    ret
+  %1 = fcmp ogt <1 x half> %v1, zeroinitializer
+  %2 = zext <1 x i1> %1 to <1 x i64>
+  ret <1 x i64> %2
+}

llvm/test/CodeGen/MIR/AMDGPU/virtreg-uses-unallocatable-class.mir

@@ -1,14 +1,13 @@
-# UNSUPPORTED: reverse_iteration
 # RUN: not llc -mtriple=amdgcn-- -mcpu=gfx900 -run-pass=none -o - %s 2>&1 | FileCheck %s
 
 # Check a diagnostic is emitted if non-allocatable classes are used
 # with virtual registers, and there's no assert.
 
-# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register named_use in function 'virtreg_unallocatable'
-# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register named_def in function 'virtreg_unallocatable'
 # CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register 0 in function 'virtreg_unallocatable'
-# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register 2 in function 'virtreg_unallocatable'
 # CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register 1 in function 'virtreg_unallocatable'
+# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register 2 in function 'virtreg_unallocatable'
+# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register named_def in function 'virtreg_unallocatable'
+# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register named_use in function 'virtreg_unallocatable'
 
 ---
 name: virtreg_unallocatable

llvm/test/CodeGen/X86/pr142513.ll

@@ -21,8 +21,7 @@ define i64 @foo(i64 %x) {
 ; X64-NEXT:    cmpl $65509, %edi # imm = 0xFFE5
 ; X64-NEXT:    je .LBB0_1
 ; X64-NEXT:  # %bb.2: # %if.end
-; X64-NEXT:    movabsq $9219572124669181952, %rax # imm = 0x7FF2800000000000
-; X64-NEXT:    addq $3, %rax
+; X64-NEXT:    movabsq $9219572124669181955, %rax # imm = 0x7FF2800000000003
 ; X64-NEXT:    retq
 ; X64-NEXT:  .LBB0_1: # %if.then
 entry: