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[AMDGPU] Prohibit load/store merge if scale_offset is set on gfx1250 (#149895)
Scaling is done on the operation size, by merging instructions we would need to generate code to scale the offset and reset the auto-scale bit. This is unclear if that would be beneficial, just disable such merge for now.
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+108
-1
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2 files changed

+108
-1
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‎llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,7 @@
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#include "AMDGPU.h"
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#include "GCNSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIDefines.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/InitializePasses.h"
@@ -1078,7 +1079,9 @@ bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI,
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if (EltOffset0 + CI.Width != EltOffset1 &&
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EltOffset1 + Paired.Width != EltOffset0)
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return false;
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if (CI.CPol != Paired.CPol)
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// Instructions with scale_offset modifier cannot be combined unless we
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// also generate a code to scale the offset and reset that bit.
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if (CI.CPol != Paired.CPol || (CI.CPol & AMDGPU::CPol::SCAL))
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return false;
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if (CI.InstClass == S_LOAD_IMM || CI.InstClass == S_BUFFER_LOAD_IMM ||
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CI.InstClass == S_BUFFER_LOAD_SGPR_IMM) {

‎llvm/test/CodeGen/AMDGPU/load-store-opt-scale-offset.mir

Lines changed: 104 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,104 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -run-pass=si-load-store-opt -o - %s | FileCheck -check-prefix=GCN %s
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---
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name: merge_global_load_dword_2_no_scale_offset
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body: |
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bb.0.entry:
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; GCN-LABEL: name: merge_global_load_dword_2_no_scale_offset
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; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec_xnull = IMPLICIT_DEF
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; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[DEF]], [[DEF1]], 0, 1, implicit $exec :: (load (s64) from `ptr addrspace(1) undef` + 4, align 4, addrspace 1)
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; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
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; GCN-NEXT: S_NOP 0, implicit [[DEF1]], implicit [[COPY]]
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%0:sreg_64_xexec_xnull = IMPLICIT_DEF
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 0, 1, implicit $exec :: (load (s32) from `float addrspace(1)* undef` + 4, basealign 4, addrspace 1)
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%3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 4, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, basealign 4, addrspace 1)
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S_NOP 0, implicit %1, implicit %2
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...
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---
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name: no_merge_global_load_dword_2_same_scale_offset
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body: |
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bb.0.entry:
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; GCN-LABEL: name: no_merge_global_load_dword_2_same_scale_offset
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; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec_xnull = IMPLICIT_DEF
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; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]], [[DEF1]], 0, 2049, implicit $exec :: (load (s32) from `ptr addrspace(1) undef` + 4, addrspace 1)
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; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]], [[DEF1]], 4, 2049, implicit $exec :: (load (s32) from `ptr addrspace(1) undef` + 8, addrspace 1)
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; GCN-NEXT: S_NOP 0, implicit [[DEF1]], implicit [[GLOBAL_LOAD_DWORD_SADDR]]
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%0:sreg_64_xexec_xnull = IMPLICIT_DEF
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 0, 2049, implicit $exec :: (load (s32) from `float addrspace(1)* undef` + 4, basealign 4, addrspace 1)
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%3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 4, 2049, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, basealign 4, addrspace 1)
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S_NOP 0, implicit %1, implicit %2
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...
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---
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name: no_merge_global_load_dword_2_different_scale_offset
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body: |
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bb.0.entry:
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; GCN-LABEL: name: no_merge_global_load_dword_2_different_scale_offset
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; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec_xnull = IMPLICIT_DEF
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; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]], [[DEF1]], 0, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef` + 4, addrspace 1)
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; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]], [[DEF1]], 4, 2048, implicit $exec :: (load (s32) from `ptr addrspace(1) undef` + 8, addrspace 1)
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; GCN-NEXT: S_NOP 0, implicit [[DEF1]], implicit [[GLOBAL_LOAD_DWORD_SADDR]]
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%0:sreg_64_xexec_xnull = IMPLICIT_DEF
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 0, 0, implicit $exec :: (load (s32) from `float addrspace(1)* undef` + 4, basealign 4, addrspace 1)
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%3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 4, 2048, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, basealign 4, addrspace 1)
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S_NOP 0, implicit %1, implicit %2
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...
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# NB: We do not currently support merging SGPR offset and SGPR+Imm offset forms
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# of S_LOAD, but the check stays the same: these cannot be merged with different
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# scale offsets.
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#
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# We also do not currently merge flat scratch instructions, although a common
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# check in the merge logic that CPol shall not be set for merge to happen.
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---
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name: merge_s_load_x1_x1_imm_no_scale_offset
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body: |
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bb.0:
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; GCN-LABEL: name: merge_s_load_x1_x1_imm_no_scale_offset
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; GCN: [[DEF:%[0-9]+]]:sgpr_64 = IMPLICIT_DEF
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; GCN-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[DEF]], 0, 0 :: (dereferenceable invariant load (s64), align 4)
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[S_LOAD_DWORDX2_IMM]].sub0
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; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0_xexec = COPY killed [[S_LOAD_DWORDX2_IMM]].sub1
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%0:sgpr_64 = IMPLICIT_DEF
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%1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0:sgpr_64, 0, 0 :: (dereferenceable invariant load (s32))
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%2:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0:sgpr_64, 4, 0 :: (dereferenceable invariant load (s32))
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...
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---
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name: no_merge_s_load_x1_x1_imm_same_scale_offset
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body: |
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bb.0:
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; GCN-LABEL: name: no_merge_s_load_x1_x1_imm_same_scale_offset
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; GCN: [[DEF:%[0-9]+]]:sgpr_64 = IMPLICIT_DEF
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; GCN-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[DEF]], 0, 2048 :: (dereferenceable invariant load (s32))
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; GCN-NEXT: [[S_LOAD_DWORD_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[DEF]], 4, 2048 :: (dereferenceable invariant load (s32))
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%0:sgpr_64 = IMPLICIT_DEF
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%1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0:sgpr_64, 0, 2048 :: (dereferenceable invariant load (s32))
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%2:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0:sgpr_64, 4, 2048 :: (dereferenceable invariant load (s32))
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...
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---
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name: no_merge_s_load_x1_x1_imm_different_scale_offset
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body: |
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bb.0:
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; GCN-LABEL: name: no_merge_s_load_x1_x1_imm_different_scale_offset
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; GCN: [[DEF:%[0-9]+]]:sgpr_64 = IMPLICIT_DEF
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; GCN-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[DEF]], 0, 0 :: (dereferenceable invariant load (s32))
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; GCN-NEXT: [[S_LOAD_DWORD_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[DEF]], 4, 2048 :: (dereferenceable invariant load (s32))
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%0:sgpr_64 = IMPLICIT_DEF
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%1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0:sgpr_64, 0, 0 :: (dereferenceable invariant load (s32))
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%2:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0:sgpr_64, 4, 2048 :: (dereferenceable invariant load (s32))
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...

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