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llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4843,10 +4843,10 @@ AMDGPUTargetLowering::foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
48434843
}
48444844

48454845
static EVT getFloatVT(EVT VT) {
4846-
return VT = VT.isVector() ? MVT::getVectorVT(MVT::getFloatingPointVT(
4847-
VT.getScalarSizeInBits()),
4848-
VT.getVectorNumElements())
4849-
: MVT::getFloatingPointVT(VT.getFixedSizeInBits());
4846+
return VT.isVector() ? MVT::getVectorVT(
4847+
MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
4848+
VT.getVectorNumElements())
4849+
: MVT::getFloatingPointVT(VT.getFixedSizeInBits());
48504850
}
48514851

48524852
static SDValue getBitwiseToSrcModifierOp(SDValue N,
@@ -4883,7 +4883,7 @@ static SDValue getBitwiseToSrcModifierOp(SDValue N,
48834883
case ISD::OR:
48844884
if ((Mask == 0x80000000u && VT.getFixedSizeInBits() == 32) ||
48854885
(Mask == 0x8000000000000000u && VT.getFixedSizeInBits() == 64)) {
4886-
SDValue Abs = DAG.getNode(ISD::ABS, SDLoc(N), FVT, BC);
4886+
SDValue Abs = DAG.getNode(ISD::FABS, SL, FVT, BC);
48874887
return DAG.getNode(ISD::FNEG, SL, FVT, Abs);
48884888
}
48894889
break;

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