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implement getting target features from backend for clang frontend
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13 files changed

+159
-200
lines changed

13 files changed

+159
-200
lines changed

‎clang/lib/Basic/Targets/PPC.cpp‎

Lines changed: 8 additions & 142 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include "clang/Basic/MacroBuilder.h"
1616
#include "clang/Basic/TargetBuiltins.h"
1717
#include "llvm/TargetParser/PPCTargetParser.h"
18+
#include <optional>
1819

1920
using namespace clang;
2021
using namespace clang::targets;
@@ -516,130 +517,15 @@ static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
516517
bool PPCTargetInfo::initFeatureMap(
517518
llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
518519
const std::vector<std::string> &FeaturesVec) const {
519-
Features["altivec"] = llvm::StringSwitch<bool>(CPU)
520-
.Case("7400", true)
521-
.Case("g4", true)
522-
.Case("7450", true)
523-
.Case("g4+", true)
524-
.Case("970", true)
525-
.Case("g5", true)
526-
.Case("pwr6", true)
527-
.Case("pwr7", true)
528-
.Case("pwr8", true)
529-
.Case("pwr9", true)
530-
.Case("ppc64", true)
531-
.Case("ppc64le", true)
532-
.Default(false);
533-
534-
Features["power9-vector"] = (CPU == "pwr9");
535-
Features["crypto"] = llvm::StringSwitch<bool>(CPU)
536-
.Case("ppc64le", true)
537-
.Case("pwr9", true)
538-
.Case("pwr8", true)
539-
.Default(false);
540-
Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
541-
.Case("ppc64le", true)
542-
.Case("pwr9", true)
543-
.Case("pwr8", true)
544-
.Default(false);
545-
Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
546-
.Case("ppc64le", true)
547-
.Case("pwr9", true)
548-
.Case("pwr8", true)
549-
.Case("pwr7", true)
550-
.Default(false);
551-
Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
552-
.Case("ppc64le", true)
553-
.Case("pwr9", true)
554-
.Case("pwr8", true)
555-
.Case("pwr7", true)
556-
.Default(false);
557-
Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
558-
.Case("ppc64le", true)
559-
.Case("pwr9", true)
560-
.Case("pwr8", true)
561-
.Default(false);
562-
Features["crbits"] = llvm::StringSwitch<bool>(CPU)
563-
.Case("ppc64le", true)
564-
.Case("pwr9", true)
565-
.Case("pwr8", true)
566-
.Default(false);
567-
Features["vsx"] = llvm::StringSwitch<bool>(CPU)
568-
.Case("ppc64le", true)
569-
.Case("pwr9", true)
570-
.Case("pwr8", true)
571-
.Case("pwr7", true)
572-
.Default(false);
573-
Features["htm"] = llvm::StringSwitch<bool>(CPU)
574-
.Case("ppc64le", true)
575-
.Case("pwr9", true)
576-
.Case("pwr8", true)
577-
.Default(false);
578-
579-
// ROP Protect is off by default.
580-
Features["rop-protect"] = false;
581-
// Privileged instructions are off by default.
582-
Features["privileged"] = false;
583520

584-
if (getTriple().isOSAIX()) {
585-
// The code generated by the -maix-small-local-[exec|dynamic]-tls option is
586-
// turned off by default.
587-
Features["aix-small-local-exec-tls"] = false;
588-
Features["aix-small-local-dynamic-tls"] = false;
589-
590-
// Turn off TLS model opt by default.
591-
Features["aix-shared-lib-tls-model-opt"] = false;
592-
}
593-
594-
Features["spe"] = llvm::StringSwitch<bool>(CPU)
595-
.Case("8548", true)
596-
.Case("e500", true)
597-
.Default(false);
598-
599-
Features["isa-v206-instructions"] = llvm::StringSwitch<bool>(CPU)
600-
.Case("ppc64le", true)
601-
.Case("pwr9", true)
602-
.Case("pwr8", true)
603-
.Case("pwr7", true)
604-
.Case("a2", true)
605-
.Default(false);
606-
607-
Features["isa-v207-instructions"] = llvm::StringSwitch<bool>(CPU)
608-
.Case("ppc64le", true)
609-
.Case("pwr9", true)
610-
.Case("pwr8", true)
611-
.Default(false);
612-
613-
Features["isa-v30-instructions"] =
614-
llvm::StringSwitch<bool>(CPU).Case("pwr9", true).Default(false);
615-
616-
Features["quadword-atomics"] =
617-
getTriple().isArch64Bit() && llvm::StringSwitch<bool>(CPU)
618-
.Case("pwr9", true)
619-
.Case("pwr8", true)
620-
.Default(false);
621-
622-
// Power10 includes all the same features as Power9 plus any features specific
623-
// to the Power10 core.
624-
if (CPU == "pwr10" || CPU == "power10") {
625-
initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
626-
addP10SpecificFeatures(Features);
627-
}
628-
629-
// Power11 includes all the same features as Power10 plus any features
630-
// specific to the Power11 core.
631-
if (CPU == "pwr11" || CPU == "power11") {
632-
initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
633-
addP11SpecificFeatures(Features);
634-
}
635-
636-
// Future CPU should include all of the features of Power 11 as well as any
637-
// additional features (yet to be determined) specific to it.
638-
if (CPU == "future") {
639-
initFeatureMap(Features, Diags, "pwr11", FeaturesVec);
640-
addFutureSpecificFeatures(Features);
641-
}
521+
const llvm::Triple &TheTriple = getTriple();
642522

523+
std::optional<llvm::StringMap<bool>> FeaturesOpt =
524+
llvm::PPC::getPPCDefaultTargetFeatures(TheTriple,
525+
llvm::PPC::normalizeCPUName(CPU));
526+
if (FeaturesOpt.has_value())
527+
Features = FeaturesOpt.value();
528+
643529
if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
644530
return false;
645531

@@ -694,26 +580,6 @@ bool PPCTargetInfo::initFeatureMap(
694580
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
695581
}
696582

697-
// Add any Power10 specific features.
698-
void PPCTargetInfo::addP10SpecificFeatures(
699-
llvm::StringMap<bool> &Features) const {
700-
Features["htm"] = false; // HTM was removed for P10.
701-
Features["paired-vector-memops"] = true;
702-
Features["mma"] = true;
703-
Features["power10-vector"] = true;
704-
Features["pcrelative-memops"] = true;
705-
Features["prefix-instrs"] = true;
706-
Features["isa-v31-instructions"] = true;
707-
}
708-
709-
// Add any Power11 specific features.
710-
void PPCTargetInfo::addP11SpecificFeatures(
711-
llvm::StringMap<bool> &Features) const {}
712-
713-
// Add features specific to the "Future" CPU.
714-
void PPCTargetInfo::addFutureSpecificFeatures(
715-
llvm::StringMap<bool> &Features) const {}
716-
717583
bool PPCTargetInfo::hasFeature(StringRef Feature) const {
718584
return llvm::StringSwitch<bool>(Feature)
719585
.Case("powerpc", true)

‎clang/test/CodeGenCXX/cxx11-thread-local-reference.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,5 +35,5 @@ int &g() { return r; }
3535
// DARWIN-LABEL: define internal cxx_fast_tlscc void @__tls_init()
3636
// CHECK: call void @[[R_INIT]]()
3737

38-
// LINUX_AIX: attributes [[ATTR0]] = { {{.*}}"target-features"{{.*}} }
38+
// LINUX_AIX: attributes [[ATTR0]] = { {{.*}} }
3939
// DARWIN: attributes [[ATTR1]] = { {{.*}}nounwind{{.*}}"target-features"{{.*}} }

‎clang/test/Driver/aix-shared-lib-tls-model-opt.c‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
// RUN: %clang -target powerpc64-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefixes=CHECK-AIX,CHECK-AIX-OFF %s
2-
// RUN: %clang -target powerpc-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefixes=CHECK-AIX,CHECK-AIX-OFF %s
1+
// RUN: %clang -target powerpc64-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-AIX %s
2+
// RUN: %clang -target powerpc-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-AIX %s
33
// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-LINUX %s
44
// RUN: %clang -target powerpc64-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-LINUX %s
55

@@ -19,9 +19,8 @@ int test(void) {
1919

2020
// CHECK-AIX: test() #0 {
2121
// CHECK-AIX: attributes #0 = {
22-
// CHECK-AIX-OFF-SAME: -aix-shared-lib-tls-model-opt
2322
// CHECK-AIX-ON-SAME: +aix-shared-lib-tls-model-opt
2423

25-
// CHECK-LINUX-NOT: {{[-+]aix-shared-lib-tls-model-opt}}
24+
// CHECK-LINUX-NOT: {{[+]aix-shared-lib-tls-model-opt}}
2625

2726
// CHECK-UNSUPPORTED-TARGET: option '-maix-shared-lib-tls-model-opt' cannot be specified on this target

‎clang/test/Driver/aix-small-local-exec-dynamic-tls.c‎

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
// RUN: %clang -target powerpc64-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-AIX-DEFAULT %s
2-
// RUN: %clang -target powerpc-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-AIX-DEFAULT %s
3-
// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-LINUX %s
4-
// RUN: %clang -target powerpc64-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-LINUX %s
1+
// RUN: %clang -target powerpc64-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-DEFAULT %s
2+
// RUN: %clang -target powerpc-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-DEFAULT %s
3+
// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-DEFAULT %s
4+
// RUN: %clang -target powerpc64-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-DEFAULT %s
55

66
// RUN: %clang -target powerpc64-unknown-aix -maix-small-local-exec-tls -S -emit-llvm \
77
// RUN: %s -o - | FileCheck %s --check-prefix=CHECK-AIX_SMALL_LOCALEXEC_TLS
@@ -39,10 +39,9 @@ int test(void) {
3939
return 0;
4040
}
4141

42-
// CHECK-AIX-DEFAULT: test() #0 {
43-
// CHECK-AIX-DEFAULT: attributes #0 = {
44-
// CHECK-AIX-DEFAULT-SAME: {{-aix-small-local-exec-tls,.*-aix-small-local-dynamic-tls|-aix-small-local-dynamic-tls,.*-aix-small-local-exec-tls}}
45-
// CHECK-LINUX-NOT: {{[-+]aix-small-local-exec-tls,.*[-+]aix-small-local-dynamic-tls|[-+]aix-small-local-dynamic-tls,.*[-+]aix-small-local-exec-tls}}
42+
// CHECK-DEFAULT: test() #0 {
43+
// CHECK-DEFAULT: attributes #0 = {
44+
// CHECK-DEFAULT-NOT: {{[-+]aix-small-local-exec-tls,.*[-+]aix-small-local-dynamic-tls|[-+]aix-small-local-dynamic-tls,.*[-+]aix-small-local-exec-tls}}
4645

4746
// CHECK-UNSUPPORTED-AIX32: option '-maix-small-local-[exec|dynamic]-tls' cannot be specified on this target
4847
// CHECK-UNSUPPORTED-LINUX: option '-maix-small-local-[exec|dynamic]-tls' cannot be specified on this target

‎clang/test/Driver/ppc-crbits.cpp‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -64,8 +64,6 @@
6464
// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mno-crbits \
6565
// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
6666

67-
// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -emit-llvm \
68-
// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
6967
// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -mcrbits \
7068
// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
7169
// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -mno-crbits \
@@ -92,8 +90,6 @@
9290
// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr8 -mno-crbits \
9391
// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
9492

95-
// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr7 -emit-llvm \
96-
// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
9793
// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr7 -mcrbits \
9894
// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
9995
// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr7 -mno-crbits \

‎clang/test/Driver/ppc-isa-features.cpp‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -5,20 +5,20 @@
55
// RUN: %clang -target powerpc64-unknown-aix -mcpu=pwr9 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR9
66
// RUN: %clang -target powerpc-unknown-aix -mcpu=pwr10 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR10
77

8-
// CHECK-PWR6: -isa-v206-instructions
9-
// CHECK-PWR6: -isa-v207-instructions
10-
// CHECK-PWR6: -isa-v30-instructions
8+
// CHECK-PWR6-NOT: isa-v206-instructions
9+
// CHECK-PWR6-NOT: isa-v207-instructions
10+
// CHECK-PWR6-NOT: isa-v30-instructions
1111

12-
// CHECK-A2: +isa-v206-instructions
13-
// CHECK-A2: -isa-v207-instructions
14-
// CHECK-A2: -isa-v30-instructions
12+
// CHECK-A2: +isa-v206-instructions
13+
// CHECK-A2-NOT: isa-v207-instructions
14+
// CHECK-A2-NOT: isa-v30-instructions
1515

16-
// CHECK-PWR7: +isa-v206-instructions
17-
// CHECK-PWR7: -isa-v207-instructions
18-
// CHECK-PWR7: -isa-v30-instructions
16+
// CHECK-PWR7: +isa-v206-instructions
17+
// CHECK-PWR7-NOT: isa-v207-instructions
18+
// CHECK-PWR7-NOT: isa-v30-instructions
1919

20-
// CHECK-PWR8: +isa-v207-instructions
21-
// CHECK-PWR8: -isa-v30-instructions
20+
// CHECK-PWR8: +isa-v207-instructions
21+
// CHECK-PWR8-NOT: isa-v30-instructions
2222

2323
// CHECK-PWR9: +isa-v207-instructions
2424
// CHECK-PWR9: +isa-v30-instructions

‎llvm/include/llvm/MC/MCSubtargetInfo.h‎

Lines changed: 25 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515

1616
#include "llvm/ADT/ArrayRef.h"
1717
#include "llvm/ADT/STLExtras.h"
18+
#include "llvm/ADT/StringMap.h"
1819
#include "llvm/ADT/StringRef.h"
1920
#include "llvm/MC/MCInstrItineraries.h"
2021
#include "llvm/MC/MCSchedule.h"
@@ -32,9 +33,8 @@ class MCInst;
3233
//===----------------------------------------------------------------------===//
3334

3435
/// Used to provide key value pairs for feature and CPU bit flags.
35-
struct SubtargetFeatureKV {
36+
struct BasicSubtargetFeatureKV {
3637
const char *Key; ///< K-V key string
37-
const char *Desc; ///< Help descriptor
3838
unsigned Value; ///< K-V integer value
3939
FeatureBitArray Implies; ///< K-V bit mask
4040

@@ -44,31 +44,49 @@ struct SubtargetFeatureKV {
4444
}
4545

4646
/// Compare routine for std::is_sorted.
47-
bool operator<(const SubtargetFeatureKV &Other) const {
47+
bool operator<(const BasicSubtargetFeatureKV &Other) const {
4848
return StringRef(Key) < StringRef(Other.Key);
4949
}
50+
BasicSubtargetFeatureKV(const char *Key, unsigned Value,
51+
FeatureBitArray Implies)
52+
: Key(Key), Value(Value), Implies(Implies) {}
53+
};
54+
55+
struct SubtargetFeatureKV : BasicSubtargetFeatureKV {
56+
const char *Desc; ///< Help descriptor
57+
SubtargetFeatureKV(const char *Key, const char *Desc, unsigned Value,
58+
FeatureBitArray Implies)
59+
: BasicSubtargetFeatureKV(Key, Value, Implies), Desc(Desc) {}
5060
};
5161

5262
//===----------------------------------------------------------------------===//
5363

5464
/// Used to provide key value pairs for feature and CPU bit flags.
55-
struct SubtargetSubTypeKV {
65+
struct BasicSubtargetSubTypeKV {
5666
const char *Key; ///< K-V key string
5767
FeatureBitArray Implies; ///< K-V bit mask
58-
FeatureBitArray TuneImplies; ///< K-V bit mask
59-
const MCSchedModel *SchedModel;
6068

6169
/// Compare routine for std::lower_bound
6270
bool operator<(StringRef S) const {
6371
return StringRef(Key) < S;
6472
}
6573

6674
/// Compare routine for std::is_sorted.
67-
bool operator<(const SubtargetSubTypeKV &Other) const {
75+
bool operator<(const BasicSubtargetSubTypeKV &Other) const {
6876
return StringRef(Key) < StringRef(Other.Key);
6977
}
7078
};
7179

80+
struct SubtargetSubTypeKV : BasicSubtargetSubTypeKV {
81+
FeatureBitArray TuneImplies; ///< K-V bit mask
82+
const MCSchedModel *SchedModel;
83+
};
84+
85+
std::optional<llvm::StringMap<bool>>
86+
getCPUDefaultTargetFeatures(StringRef CPU,
87+
ArrayRef<BasicSubtargetSubTypeKV> ProcDesc,
88+
ArrayRef<BasicSubtargetFeatureKV> ProcFeatures);
89+
7290
//===----------------------------------------------------------------------===//
7391
///
7492
/// Generic base class for all target subtargets.

‎llvm/include/llvm/TargetParser/PPCTargetParser.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,9 @@
1414
#ifndef LLVM_TARGETPARSER_PPCTARGETPARSER_H
1515
#define LLVM_TARGETPARSER_PPCTARGETPARSER_H
1616

17+
#include "llvm/ADT/StringMap.h"
1718
#include "llvm/ADT/StringRef.h"
19+
#include "llvm/MC/MCSubtargetInfo.h"
1820
#include "llvm/TargetParser/Triple.h"
1921

2022
namespace llvm {
@@ -34,6 +36,9 @@ StringRef getNormalizedPPCTuneCPU(const Triple &T, StringRef CPUName = "");
3436
// For PPC, there are some cpu names for same CPU, like pwr10 and power10,
3537
// normalize them.
3638
StringRef normalizeCPUName(StringRef CPUName);
39+
40+
std::optional<llvm::StringMap<bool>>
41+
getPPCDefaultTargetFeatures(const Triple &T, StringRef CPUName);
3742
} // namespace PPC
3843
} // namespace llvm
3944

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