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1 parent 12e1667 commit 9860e14Copy full SHA for 9860e14
llvm/test/MC/RISCV/xqciio-invalid.s
@@ -29,7 +29,8 @@ qc.inw x23, x17
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# CHECK-MINUS: :[[@LINE+1]]:13: error: invalid operand for instruction
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qc.inw x23, x17
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-# CHECK: :[[@LINE+1]]:8: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:8: error: register must be a GPR excluding zero (x0)
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+# CHECK-MINUS: :[[@LINE+1]]:8: error: invalid operand for instruction
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qc.inw x0, 16380(x17)
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# CHECK-PLUS: :[[@LINE+1]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 16380]
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