Remove SVE handling and add pattern to compensate

Author: dheaton-arm

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -20708,42 +20708,31 @@ static SDValue performFMACombine(SDNode *N,
   // fma(a, b, neg(c)) -> fnmls(a, b, c)
   // fma(neg(a), b, neg(c)) -> fnmla(a, b, c)
   // fma(a, neg(b), neg(c)) -> fnmla(a, b, c)
-  if (!VT.isVector() || !DAG.getTargetLoweringInfo().isTypeLegal(VT) ||
+  if (!VT.isFixedLengthVector() ||
+      !DAG.getTargetLoweringInfo().isTypeLegal(VT) ||
       !Subtarget->isSVEorStreamingSVEAvailable() ||
       OpC.getOpcode() != ISD::FNEG) {
     return SDValue();
   }
 
   SDValue Pg = getPredicateForVector(DAG, DL, VT);
-  EVT ContainerVT =
-      VT.isFixedLengthVector() ? getContainerForFixedLengthVector(DAG, VT) : VT;
-  OpC = VT.isFixedLengthVector()
-            ? convertToScalableVector(DAG, ContainerVT, OpC.getOperand(0))
-            : OpC->getOperand(0);
-  OpC = DAG.getNode(AArch64ISD::FNEG_MERGE_PASSTHRU, DL, ContainerVT, Pg, OpC,
-                    DAG.getUNDEF(ContainerVT));
-
-  if (OpB.getOpcode() == ISD::FNEG) {
-    std::swap(OpA, OpB);
-  }
-
-  if (OpA.getOpcode() == ISD::FNEG) {
-    OpA = VT.isFixedLengthVector()
-              ? convertToScalableVector(DAG, ContainerVT, OpA.getOperand(0))
-              : OpA->getOperand(0);
-    OpA = DAG.getNode(AArch64ISD::FNEG_MERGE_PASSTHRU, DL, ContainerVT, Pg, OpA,
-                      DAG.getUNDEF(ContainerVT));
-  } else if (VT.isFixedLengthVector()) {
-    OpA = convertToScalableVector(DAG, ContainerVT, OpA);
-  }
-
-  if (VT.isFixedLengthVector()) {
-    OpB = convertToScalableVector(DAG, ContainerVT, OpB);
-    SDValue ScalableRes =
-        DAG.getNode(AArch64ISD::FMA_PRED, DL, ContainerVT, Pg, OpA, OpB, OpC);
-    return convertFromScalableVector(DAG, VT, ScalableRes);
-  }
-  return DAG.getNode(AArch64ISD::FMA_PRED, DL, VT, Pg, OpA, OpB, OpC);
+  EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
+  OpC =
+      DAG.getNode(AArch64ISD::FNEG_MERGE_PASSTHRU, DL, ContainerVT, Pg,
+                  convertToScalableVector(DAG, ContainerVT, OpC.getOperand(0)),
+                  DAG.getUNDEF(ContainerVT));
+
+  OpA = OpA.getOpcode() == ISD::FNEG
+            ? DAG.getNode(
+                  AArch64ISD::FNEG_MERGE_PASSTHRU, DL, ContainerVT, Pg,
+                  convertToScalableVector(DAG, ContainerVT, OpA.getOperand(0)),
+                  DAG.getUNDEF(ContainerVT))
+            : convertToScalableVector(DAG, ContainerVT, OpA);
+
+  OpB = convertToScalableVector(DAG, ContainerVT, OpB);
+  SDValue ScalableRes =
+      DAG.getNode(AArch64ISD::FMA_PRED, DL, ContainerVT, Pg, OpA, OpB, OpC);
+  return convertFromScalableVector(DAG, VT, ScalableRes);
 }
 
 static bool hasPairwiseAdd(unsigned Opcode, EVT VT, bool FullFP16) {

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

@@ -462,6 +462,7 @@ def AArch64fmlsidx : PatFrags<(ops node:$acc, node:$op1, node:$op2, node:$idx),
 def AArch64fnmla_p : PatFrags<(ops node:$pg, node:$za, node:$zn, node:$zm),
                               [(int_aarch64_sve_fnmla_u node:$pg, node:$za, node:$zn, node:$zm),
                                (AArch64fma_p node:$pg, (AArch64fneg_mt node:$pg, node:$zn, (undef)), node:$zm, (AArch64fneg_mt node:$pg, node:$za, (undef))),
+                               (AArch64fma_p node:$pg, node:$zn, (AArch64fneg_mt node:$pg, node:$zm, (undef)), (AArch64fneg_mt node:$pg, node:$za, (undef))),
                                (AArch64fneg_mt_nsz node:$pg, (AArch64fma_p node:$pg, node:$zn, node:$zm, node:$za), (undef))]>;
 
 def AArch64fnmls_p : PatFrags<(ops node:$pg, node:$za, node:$zn, node:$zm),