@@ -772,24 +772,24 @@ bool SIPreEmitPeephole::run(MachineFunction &MF) {
772772 // side effects.
773773
774774 // Perform the extra MF scans only for supported archs
775- if (ST.hasGFX940Insts ()) {
776- for (MachineBasicBlock &MBB : MF) {
777- // Unpack packed instructions overlapped by MFMAs. This allows the
778- // compiler to co-issue unpacked instructions with MFMA
779- auto SchedModel = TII-> getSchedModel ();
780- SetVector<MachineInstr *> InstrsToUnpack ;
781- for ( auto &MI : make_early_inc_range (MBB. instrs ())) {
782- if (! SIInstrInfo::isMFMA (MI))
783- continue ;
784- const MCSchedClassDesc *SchedClassDesc =
785- SchedModel. resolveSchedClass (&MI);
786- uint16_t NumMFMACycles =
787- SchedModel. getWriteProcResBegin (SchedClassDesc)-> ReleaseAtCycle ;
788- collectUnpackingCandidates (MI, InstrsToUnpack, NumMFMACycles) ;
789- }
790- for (MachineInstr *MI : InstrsToUnpack) {
791- performF32Unpacking ( *MI);
792- }
775+ if (! ST.hasGFX940Insts ())
776+ return Changed;
777+ for (MachineBasicBlock &MBB : MF) {
778+ // Unpack packed instructions overlapped by MFMAs. This allows the
779+ // compiler to co-issue unpacked instructions with MFMA
780+ auto SchedModel = TII-> getSchedModel () ;
781+ SetVector<MachineInstr *> InstrsToUnpack;
782+ for ( auto &MI : make_early_inc_range (MBB. instrs ())) {
783+ if (! SIInstrInfo::isMFMA (MI))
784+ continue ;
785+ const MCSchedClassDesc *SchedClassDesc =
786+ SchedModel. resolveSchedClass (&MI);
787+ uint16_t NumMFMACycles =
788+ SchedModel. getWriteProcResBegin (SchedClassDesc)-> ReleaseAtCycle ;
789+ collectUnpackingCandidates (MI, InstrsToUnpack, NumMFMACycles);
790+ }
791+ for (MachineInstr *MI : InstrsToUnpack) {
792+ performF32Unpacking (*MI);
793793 }
794794 }
795795
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