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Update tests
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9 files changed

+47
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‎llvm/test/TableGen/GlobalISelEmitter/HwModes.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,8 @@ class MyTargetGenericInstruction : GenericInstruction {
1313
//def Has32 : Predicate<"Subtarget->has32()">;
1414
def Has64 : Predicate<"Subtarget->has64()">;
1515

16-
//def Mode32 : HwMode<"+a", [Has32]>;
17-
def Mode64 : HwMode<"+b", [Has64]>;
16+
//def Mode32 : HwMode<[Has32]>;
17+
def Mode64 : HwMode<[Has64]>;
1818

1919
def ModeVT : ValueTypeByHwMode<[DefaultMode, Mode64],
2020
[i32, i64]>;

‎llvm/test/TableGen/HwModeBitSet.td‎

Lines changed: 30 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,17 @@ def TestTarget : Target {
1111
let InstructionSet = TestTargetInstrInfo;
1212
}
1313

14-
def TestMode : HwMode<"+feat", []>;
15-
def TestMode1 : HwMode<"+feat1", []>;
16-
def TestMode2 : HwMode<"+feat2", []>;
14+
def Feat1 : SubtargetFeature<"feat1", "HasFeat1", "true", "enable feature 1">;
15+
def Feat2 : SubtargetFeature<"feat2", "HasFeat2", "true", "enable feature 2">;
16+
17+
def HasFeat1 : Predicate<"Subtarget->hasFeat1()">,
18+
AssemblerPredicate<(all_of Feat1)>;
19+
def HasFeat2 : Predicate<"Subtarget->hasFeat2()">,
20+
AssemblerPredicate<(all_of Feat1)>;
21+
22+
def TestMode : HwMode<[HasFeat1]>;
23+
def TestMode1 : HwMode<[HasFeat2]>;
24+
def TestMode2 : HwMode<[HasFeat1, HasFeat2]>;
1725

1826
class MyReg<string n>
1927
: Register<n> {
@@ -120,13 +128,26 @@ def foo : Instruction {
120128
let AsmString = "foo $factor";
121129
}
122130

131+
// CHECK-SUBTARGET-LABEL: unsigned TestTargetGenMCSubtargetInfo::getHwModeSet() const {
132+
// CHECK-SUBTARGET{LITERAL}:[[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
133+
// CHECK-SUBTARGET-NEXT: // Collect HwModes and store them as a bit set.
134+
// CHECK-SUBTARGET-NEXT: unsigned Modes = 0;
135+
// CHECK-SUBTARGET-NEXT: if (FB[TestTarget::Feat1]) Modes |= (1 << 0);
136+
// CHECK-SUBTARGET-NEXT: if (FB[TestTarget::Feat1]) Modes |= (1 << 1);
137+
// CHECK-SUBTARGET-NEXT: if (FB[TestTarget::Feat1] && FB[TestTarget::Feat1]) Modes |= (1 << 2);
138+
// CHECK-SUBTARGET-NEXT: return Modes;
139+
// CHECK-SUBTARGET-NEXT: }
140+
123141
// CHECK-SUBTARGET-LABEL: unsigned TestTargetGenSubtargetInfo::getHwModeSet() const {
124-
// CHECK-SUBTARGET: unsigned Modes = 0;
125-
// CHECK-SUBTARGET: if (checkFeatures("+feat")) Modes |= (1 << 0);
126-
// CHECK-SUBTARGET: if (checkFeatures("+feat1")) Modes |= (1 << 1);
127-
// CHECK-SUBTARGET: if (checkFeatures("+feat2")) Modes |= (1 << 2);
128-
// CHECK-SUBTARGET: return Modes;
129-
// CHECK-SUBTARGET: }
142+
// CHECK-SUBTARGET{LITERAL}:[[maybe_unused]] const auto *Subtarget =
143+
// CHECK-SUBTARGET-NEXT: static_cast<const TestTargetSubtarget *>(this);
144+
// CHECK-SUBTARGET-NEXT: // Collect HwModes and store them as a bit set.
145+
// CHECK-SUBTARGET-NEXT: unsigned Modes = 0;
146+
// CHECK-SUBTARGET-NEXT: if ((Subtarget->hasFeat1())) Modes |= (1 << 0);
147+
// CHECK-SUBTARGET-NEXT: if ((Subtarget->hasFeat2())) Modes |= (1 << 1);
148+
// CHECK-SUBTARGET-NEXT: if ((Subtarget->hasFeat1()) && (Subtarget->hasFeat2())) Modes |= (1 << 2);
149+
// CHECK-SUBTARGET-NEXT: return Modes;
150+
// CHECK-SUBTARGET-NEXT: }
130151
// CHECK-SUBTARGET-LABEL: unsigned TestTargetGenSubtargetInfo::getHwMode(enum HwModeType type) const {
131152
// CHECK-SUBTARGET: unsigned Modes = getHwModeSet();
132153
// CHECK-SUBTARGET: if (!Modes)

‎llvm/test/TableGen/HwModeEncodeAPInt.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,9 @@ def Myi32 : Operand<i32> {
1717
def HasA : Predicate<"Subtarget->hasA()">;
1818
def HasB : Predicate<"Subtarget->hasB()">;
1919

20-
def ModeA : HwMode<"+a", [HasA]>; // Mode 1
21-
def ModeB : HwMode<"+b", [HasB]>; // Mode 2
22-
def ModeC : HwMode<"+c", []>; // Mode 3
20+
def ModeA : HwMode<[HasA]>; // Mode 1
21+
def ModeB : HwMode<[HasB]>; // Mode 2
22+
def ModeC : HwMode<[]>; // Mode 3
2323

2424

2525
def fooTypeEncDefault : InstructionEncoding {

‎llvm/test/TableGen/HwModeEncodeDecode.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@ def Myi32 : Operand<i32> {
1616
def HasA : Predicate<"Subtarget->hasA()">;
1717
def HasB : Predicate<"Subtarget->hasB()">;
1818

19-
def ModeA : HwMode<"+a", [HasA]>;
20-
def ModeB : HwMode<"+b", [HasB]>;
19+
def ModeA : HwMode<[HasA]>;
20+
def ModeB : HwMode<[HasB]>;
2121

2222

2323
def fooTypeEncA : InstructionEncoding {

‎llvm/test/TableGen/HwModeEncodeDecode2.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,8 @@ def Myi32 : Operand<i32> {
2020
def HasA : Predicate<"Subtarget->hasA()">;
2121
def HasB : Predicate<"Subtarget->hasB()">;
2222

23-
def ModeA : HwMode<"+a", [HasA]>;
24-
def ModeB : HwMode<"+b", [HasB]>;
23+
def ModeA : HwMode<[HasA]>;
24+
def ModeB : HwMode<[HasB]>;
2525

2626

2727
def fooTypeEncA : InstructionEncoding {

‎llvm/test/TableGen/HwModeEncodeDecode3.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,9 +22,9 @@ def Myi32 : Operand<i32> {
2222
def HasA : Predicate<"Subtarget->hasA()">;
2323
def HasB : Predicate<"Subtarget->hasB()">;
2424

25-
def ModeA : HwMode<"+a", [HasA]>; // Mode 1
26-
def ModeB : HwMode<"+b", [HasB]>; // Mode 2
27-
def ModeC : HwMode<"+c", []>; // Mode 3
25+
def ModeA : HwMode<[HasA]>; // Mode 1
26+
def ModeB : HwMode<[HasB]>; // Mode 2
27+
def ModeC : HwMode<[]>; // Mode 3
2828

2929

3030
def fooTypeEncDefault : InstructionEncoding {

‎llvm/test/TableGen/HwModeSelect.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,8 @@ def TestClass : RegisterClass<"TestTarget", [i32], 32, (add TestReg)>;
2121
def HasFeat1 : Predicate<"Subtarget->hasFeat1()">;
2222
def HasFeat2 : Predicate<"Subtarget->hasFeat2()">;
2323

24-
def TestMode1 : HwMode<"+feat1", [HasFeat1]>;
25-
def TestMode2 : HwMode<"+feat2", [HasFeat2]>;
24+
def TestMode1 : HwMode<[HasFeat1]>;
25+
def TestMode2 : HwMode<[HasFeat2]>;
2626

2727
// CHECK: error: assertion failed: The Objects and Modes lists must be the same length
2828
// CHECK: [[FILE]]:[[@LINE+1]]:5: error: assertion failed in this record

‎llvm/test/TableGen/HwModeSubRegs.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ include "llvm/Target/Target.td"
33

44
def HasFeat : Predicate<"Subtarget->hasFeat()">;
55

6-
def TestMode : HwMode<"+feat1", [HasFeat]>;
6+
def TestMode : HwMode<[HasFeat]>;
77

88
class MyReg<string n>
99
: Register<n> {

‎llvm/test/TableGen/VarLenEncoderHwModes.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,8 @@ def GR64 : RegisterOperand<RegClass>;
1919
def HasA : Predicate<"Subtarget->hasA()">;
2020
def HasB : Predicate<"Subtarget->hasB()">;
2121

22-
def ModeA : HwMode<"+a", [HasA]>;
23-
def ModeB : HwMode<"+b", [HasB]>;
22+
def ModeA : HwMode<[HasA]>;
23+
def ModeB : HwMode<[HasB]>;
2424

2525
def fooTypeEncA : InstructionEncoding {
2626
dag Inst = (descend

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