dont rename GCNNSAReassignID

vikramRH · vikramRH · commit 98baed7b37de · 2025-02-17T15:54:42.000+05:30
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -449,7 +449,7 @@ void initializeAMDGPUOpenCLEnqueuedBlockLoweringLegacyPass(PassRegistry &);
 extern char &AMDGPUOpenCLEnqueuedBlockLoweringLegacyID;
 
 void initializeGCNNSAReassignLegacyPass(PassRegistry &);
-extern char &GCNNSAReassignLegacyID;
+extern char &GCNNSAReassignID;
 
 void initializeGCNPreRALongBranchRegLegacyPass(PassRegistry &);
 extern char &GCNPreRALongBranchRegID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1521,7 +1521,7 @@ void GCNPassConfig::addOptimizedRegAlloc() {
 
 bool GCNPassConfig::addPreRewrite() {
   if (EnableRegReassign)
-    addPass(&GCNNSAReassignLegacyID);
+    addPass(&GCNNSAReassignID);
   return true;
 }
 
diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
@@ -110,7 +110,7 @@ INITIALIZE_PASS_END(GCNNSAReassignLegacy, DEBUG_TYPE, "GCN NSA Reassign", false,
 
 char GCNNSAReassignLegacy::ID = 0;
 
-char &llvm::GCNNSAReassignLegacyID = GCNNSAReassignLegacy::ID;
+char &llvm::GCNNSAReassignID = GCNNSAReassignLegacy::ID;
 
 bool GCNNSAReassignImpl::tryAssignRegisters(
     SmallVectorImpl<LiveInterval *> &Intervals, unsigned StartReg) const {

Original file line number	Diff line number	Diff line change
`@@ -1521,7 +1521,7 @@ void GCNPassConfig::addOptimizedRegAlloc() {`
`1521`	`1521`
`1522`	`1522`	`bool GCNPassConfig::addPreRewrite() {`
`1523`	`1523`	`if (EnableRegReassign)`
`1524`		`- addPass(&GCNNSAReassignLegacyID);`
	`1524`	`+ addPass(&GCNNSAReassignID);`
`1525`	`1525`	`return true;`
`1526`	`1526`	`}`
`1527`	`1527`