Skip to content

Commit 98bc048

Browse files
lei137lei137
committed
udpate to only add support for v4i32 types
1 parent 894b8a0 commit 98bc048

File tree

3 files changed

+18
-86
lines changed

3 files changed

+18
-86
lines changed

‎llvm/include/llvm/IR/IntrinsicsPowerPC.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1359,10 +1359,10 @@ def int_ppc_vsx_lxvp :
13591359
DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty],
13601360
[IntrReadMem, IntrArgMemOnly]>;
13611361
def int_ppc_vsx_lxvrl :
1362-
DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_ptr_ty, llvm_i64_ty],
1362+
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i64_ty],
13631363
[IntrReadMem, IntrArgMemOnly]>;
13641364
def int_ppc_vsx_lxvrll :
1365-
DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_ptr_ty, llvm_i64_ty],
1365+
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i64_ty],
13661366
[IntrReadMem, IntrArgMemOnly]>;
13671367
def int_ppc_vsx_lxvprl :
13681368
DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty, llvm_i64_ty],
@@ -1390,10 +1390,10 @@ def int_ppc_vsx_stxvp :
13901390
Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty], [IntrWriteMem,
13911391
IntrArgMemOnly]>;
13921392
def int_ppc_vsx_stxvrl :
1393-
Intrinsic<[], [llvm_anyvector_ty, llvm_ptr_ty, llvm_i64_ty],
1393+
Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
13941394
[IntrWriteMem, IntrArgMemOnly]>;
13951395
def int_ppc_vsx_stxvrll :
1396-
Intrinsic<[], [llvm_anyvector_ty, llvm_ptr_ty, llvm_i64_ty],
1396+
Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
13971397
[IntrWriteMem, IntrArgMemOnly]>;
13981398
def int_ppc_vsx_stxvprl :
13991399
Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem,

‎llvm/lib/Target/PowerPC/PPCInstrFuture.td‎

Lines changed: 14 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -193,22 +193,20 @@ let Predicates = [HasVSX, IsISAFuture] in {
193193
"vucmprlh $VRT, $VRA, $VRB", []>;
194194
}
195195

196+
//---------------------------- Anonymous Patterns ----------------------------//
197+
196198
// Load/Store VSX Vector with Right Length Left-justified.
197-
foreach Ty = [v4i32, v2i64] in {
198-
def : Pat<(Ty (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)),
199-
(LXVRL $RA, $RB)>;
200-
def : Pat<(Ty (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)),
201-
(LXVRLL $RA, $RB)>;
202-
def : Pat<(int_ppc_vsx_stxvrl Ty:$XT, addr:$RA, i64:$RB),
203-
(STXVRL $XT, $RA, $RB)>;
204-
def : Pat<(int_ppc_vsx_stxvrll Ty:$XT, addr:$RA, i64:$RB),
205-
(STXVRLL $XT, $RA, $RB)>;
206-
}
199+
def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
200+
def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
201+
def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB), (STXVRL $XT, $RA,
202+
$RB)>;
203+
def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB), (STXVRLL $XT, $RA,
204+
$RB)>;
207205

208206
// Load/Store VSX Vector pair with Right Length Left-justified.
209-
def : Pat<(v256i1(int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
210-
def : Pat<(v256i1(int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
211-
def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB),
212-
(STXVPRL $XTp, $RA, $RB)>;
213-
def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB),
214-
(STXVPRLL $XTp, $RA, $RB)>;
207+
def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
208+
def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
209+
def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRL $XTp,
210+
$RA, $RB)>;
211+
def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRLL $XTp,
212+
$RA, $RB)>;

‎llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll‎

Lines changed: 0 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -72,72 +72,6 @@ entry:
7272
}
7373
declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
7474

75-
; Test for load/store to/from v2i64.
76-
77-
define <2 x i64> @testLXVRL2(ptr %a, i64 %b) {
78-
; CHECK-LABEL: testLXVRL2:
79-
; CHECK: # %bb.0: # %entry
80-
; CHECK-NEXT: lxvrl v2, r3, r4
81-
; CHECK-NEXT: blr
82-
;
83-
; AIX-LABEL: testLXVRL2:
84-
; AIX: # %bb.0: # %entry
85-
; AIX-NEXT: lxvrl v2, r3, r4
86-
; AIX-NEXT: blr
87-
entry:
88-
%0 = tail call <2 x i64> @llvm.ppc.vsx.lxvrl.v2i64(ptr %a, i64 %b)
89-
ret <2 x i64> %0
90-
}
91-
declare <2 x i64> @llvm.ppc.vsx.lxvrl.v2i64(ptr, i64)
92-
93-
define <2 x i64> @testLXVRLL2(ptr %a, i64 %b) {
94-
; CHECK-LABEL: testLXVRLL2:
95-
; CHECK: # %bb.0: # %entry
96-
; CHECK-NEXT: lxvrll v2, r3, r4
97-
; CHECK-NEXT: blr
98-
;
99-
; AIX-LABEL: testLXVRLL2:
100-
; AIX: # %bb.0: # %entry
101-
; AIX-NEXT: lxvrll v2, r3, r4
102-
; AIX-NEXT: blr
103-
entry:
104-
%0 = tail call <2 x i64> @llvm.ppc.vsx.lxvrll.v2i64(ptr %a, i64 %b)
105-
ret <2 x i64> %0
106-
}
107-
declare <2 x i64> @llvm.ppc.vsx.lxvrll.v2i64(ptr, i64)
108-
109-
define void @testSTXVRL2(<2 x i64> %a, ptr %b, i64 %c) {
110-
; CHECK-LABEL: testSTXVRL2:
111-
; CHECK: # %bb.0: # %entry
112-
; CHECK-NEXT: stxvrl v2, r5, r6
113-
; CHECK-NEXT: blr
114-
;
115-
; AIX-LABEL: testSTXVRL2:
116-
; AIX: # %bb.0: # %entry
117-
; AIX-NEXT: stxvrl v2, r3, r4
118-
; AIX-NEXT: blr
119-
entry:
120-
tail call void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64> %a, ptr %b, i64 %c)
121-
ret void
122-
}
123-
declare void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64>, ptr, i64)
124-
125-
define void @testSTXVRLL2(<2 x i64> %a, ptr %b, i64 %c) {
126-
; CHECK-LABEL: testSTXVRLL2:
127-
; CHECK: # %bb.0: # %entry
128-
; CHECK-NEXT: stxvrll v2, r5, r6
129-
; CHECK-NEXT: blr
130-
;
131-
; AIX-LABEL: testSTXVRLL2:
132-
; AIX: # %bb.0: # %entry
133-
; AIX-NEXT: stxvrll v2, r3, r4
134-
; AIX-NEXT: blr
135-
entry:
136-
tail call void @llvm.ppc.vsx.stxvrll.v2i64(<2 x i64> %a, ptr %b, i64 %c)
137-
ret void
138-
}
139-
declare void @llvm.ppc.vsx.stxvrll.v2i64(<2 x i64>, ptr, i64)
140-
14175
; Test for load/store vectore pair.
14276

14377
define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {

0 commit comments

Comments
 (0)