[ARM] Auto-decode MVE instructions with VCCR output operand (NFC)

Author: s-barannikov

llvm/lib/Target/ARM/ARMInstrMVE.td

@@ -4128,11 +4128,12 @@ defm MVE_VMINNMAf16 : MVE_VMINNMA<MVE_v8f16, 0b1>;
 
 // start of MVE compares
 
+// Base class for comparing two vector registers
 class MVE_VCMPqq<string suffix, bit bit_28, bits<2> bits_21_20,
                  VCMPPredicateOperand predtype, bits<2> vecsize, list<dag> pattern=[]>
   : MVE_p<(outs VCCR:$P0), (ins MQPR:$Qn, MQPR:$Qm, predtype:$fc),
            NoItinerary, "vcmp", suffix, "$fc, $Qn, $Qm", vpred_n, "", vecsize, pattern> {
-  // Base class for comparing two vector registers
+  bits<0> P0;
   bits<3> fc;
   bits<4> Qn;
   bits<4> Qm;
@@ -4152,16 +4153,6 @@ class MVE_VCMPqq<string suffix, bit bit_28, bits<2> bits_21_20,
   let Inst{0} = fc{1};
 
   let Constraints = "";
-
-  // We need a custom decoder method for these instructions because of
-  // the output VCCR operand, which isn't encoded in the instruction
-  // bits anywhere (there is only one choice for it) but has to be
-  // included in the MC operands so that codegen will be able to track
-  // its data flow between instructions, spill/reload it when
-  // necessary, etc. There seems to be no way to get the Tablegen
-  // decoder to emit an operand that isn't affected by any instruction
-  // bit.
-  let DecoderMethod = "DecodeMVEVCMP<false," # predtype.DecoderMethod # ">";
   let validForTailPredication = 1;
 }
 
@@ -4202,11 +4193,12 @@ def MVE_VCMPs8  : MVE_VCMPqqs<"s8",  0b00>;
 def MVE_VCMPs16 : MVE_VCMPqqs<"s16", 0b01>;
 def MVE_VCMPs32 : MVE_VCMPqqs<"s32", 0b10>;
 
+// Base class for comparing a vector register with a scalar
 class MVE_VCMPqr<string suffix, bit bit_28, bits<2> bits_21_20,
                  VCMPPredicateOperand predtype, bits<2> vecsize, list<dag> pattern=[]>
   : MVE_p<(outs VCCR:$P0), (ins MQPR:$Qn, GPRwithZR:$Rm, predtype:$fc),
            NoItinerary, "vcmp", suffix, "$fc, $Qn, $Rm", vpred_n, "", vecsize, pattern> {
-  // Base class for comparing a vector register with a scalar
+  bits<0> P0;
   bits<3> fc;
   bits<4> Qn;
   bits<4> Rm;
@@ -4225,8 +4217,6 @@ class MVE_VCMPqr<string suffix, bit bit_28, bits<2> bits_21_20,
   let Inst{3-0} = Rm{3-0};
 
   let Constraints = "";
-  // Custom decoder method, for the same reason as MVE_VCMPqq
-  let DecoderMethod = "DecodeMVEVCMP<true," # predtype.DecoderMethod # ">";
   let validForTailPredication = 1;
 }
 
@@ -5762,6 +5752,7 @@ let isReMaterializable = 1 in
 class MVE_VCTPInst<string suffix, bits<2> size, list<dag> pattern=[]>
   : MVE_p<(outs VCCR:$P0), (ins rGPR:$Rn), NoItinerary, "vctp", suffix,
           "$Rn", vpred_n, "", size, pattern> {
+  bits<0> P0;
   bits<4> Rn;
 
   let Inst{28-27} = 0b10;
@@ -5773,7 +5764,6 @@ class MVE_VCTPInst<string suffix, bits<2> size, list<dag> pattern=[]>
   let Unpredictable{10-0} = 0b11111111111;
 
   let Constraints = "";
-  let DecoderMethod = "DecodeMveVCTP";
   let validForTailPredication = 1;
 }
 
@@ -6813,14 +6803,15 @@ let Predicates = [HasMVEFloat] in {
 
 def MVE_VPNOT : MVE_p<(outs VCCR:$P0), (ins VCCR:$P0_in), NoItinerary,
                       "vpnot", "", "", vpred_n, "", 0b00, []> {
+  bits<0> P0;
+  bits<0> P0_in;
   let Inst{31-0} = 0b11111110001100010000111101001101;
   let Unpredictable{19-17} = 0b111;
   let Unpredictable{12} = 0b1;
   let Unpredictable{7} = 0b1;
   let Unpredictable{5} = 0b1;
 
   let Constraints = "";
-  let DecoderMethod = "DecodeMVEVPNOT";
 }
 
 let Predicates = [HasMVEInt] in {

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

@@ -602,6 +602,12 @@ static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeVCCRRegisterClass(MCInst &Inst,
+                                            const MCDisassembler *Decoder) {
+  Inst.addOperand(MCOperand::createReg(ARM::VPR));
+  return MCDisassembler::Success;
+}
+
 // Operand decoding functions.
 
 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
@@ -5992,62 +5998,6 @@ static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
   return S;
 }
 
-template <bool scalar, OperandDecoder predicate_decoder>
-static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                  const MCDisassembler *Decoder) {
-  DecodeStatus S = MCDisassembler::Success;
-  Inst.addOperand(MCOperand::createReg(ARM::VPR));
-  unsigned Qn = fieldFromInstruction(Insn, 17, 3);
-  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
-    return MCDisassembler::Fail;
-
-  unsigned fc;
-
-  if (scalar) {
-    fc = fieldFromInstruction(Insn, 12, 1) << 2 |
-         fieldFromInstruction(Insn, 7, 1) |
-         fieldFromInstruction(Insn, 5, 1) << 1;
-    unsigned Rm = fieldFromInstruction(Insn, 0, 4);
-    if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
-      return MCDisassembler::Fail;
-  } else {
-    fc = fieldFromInstruction(Insn, 12, 1) << 2 |
-         fieldFromInstruction(Insn, 7, 1) |
-         fieldFromInstruction(Insn, 0, 1) << 1;
-    unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |
-                  fieldFromInstruction(Insn, 1, 3);
-    if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
-      return MCDisassembler::Fail;
-  }
-
-  if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
-    return MCDisassembler::Fail;
-
-  Check(S, DecodeVpredNOperand(Inst, Decoder));
-  return S;
-}
-
-static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                  const MCDisassembler *Decoder) {
-  DecodeStatus S = MCDisassembler::Success;
-  Inst.addOperand(MCOperand::createReg(ARM::VPR));
-  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
-  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
-    return MCDisassembler::Fail;
-  Check(S, DecodeVpredNOperand(Inst, Decoder));
-  return S;
-}
-
-static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address,
-                                   const MCDisassembler *Decoder) {
-  DecodeStatus S = MCDisassembler::Success;
-  Inst.addOperand(MCOperand::createReg(ARM::VPR));
-  Inst.addOperand(MCOperand::createReg(ARM::VPR));
-  Check(S, DecodeVpredNOperand(Inst, Decoder));
-  return S;
-}
-
 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
                                         uint64_t Address,
                                         const MCDisassembler *Decoder) {