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[RISCV] Rename MIPS_PREFETCH->MIPS_PREF. NFC (#154062)
This matches the instruction's assembler mnemonic.
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llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -129,20 +129,20 @@ class Mips_prefetch_ri<dag outs, dag ins, string opcodestr, string argstr>
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// MIPS extensions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasVendorXMIPSCBOP] ,DecoderNamespace = "Xmipscbop" in {
132-
def MIPS_PREFETCH : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
133-
"mips.pref", "$hint, ${imm9}(${rs1})">,
134-
Sched<[]>;
132+
def MIPS_PREF : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
133+
"mips.pref", "$hint, ${imm9}(${rs1})">,
134+
Sched<[]>;
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}
136136

137137
let Predicates = [HasVendorXMIPSCBOP] in {
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// Prefetch Data Write.
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def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),
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(i32 1), timm, (i32 1)),
141-
(MIPS_PREFETCH GPR:$rs1, uimm9:$imm9, 9)>;
141+
(MIPS_PREF GPR:$rs1, uimm9:$imm9, 9)>;
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// Prefetch Data Read.
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def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),
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(i32 0), timm, (i32 1)),
145-
(MIPS_PREFETCH GPR:$rs1, uimm9:$imm9, 8)>;
145+
(MIPS_PREF GPR:$rs1, uimm9:$imm9, 8)>;
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}
147147

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let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0, mayStore = 0,

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -589,7 +589,7 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
589589
(Lo12 & 0b11111) != 0) {
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// Prefetch instructions require the offset to be 32 byte aligned.
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
592-
} else if (Opc == RISCV::MIPS_PREFETCH && !isUInt<9>(Val)) {
592+
} else if (Opc == RISCV::MIPS_PREF && !isUInt<9>(Val)) {
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// MIPS Prefetch instructions require the offset to be 9 bits encoded.
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
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} else if ((Opc == RISCV::PseudoRV32ZdinxLD ||

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