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[RISCV][llvm] Support fixed-length vector inline assembly constraints (#150724)
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3 files changed

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‎clang/test/CodeGen/RISCV/riscv-inline-asm-fixed-length-vector.c

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
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// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv32 -target-feature +v \
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// RUN: -mvscale-min=2 -mvscale-max=2 -O2 -emit-llvm %s -o - \
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// RUN: | FileCheck %s
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// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
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// RUN: -mvscale-min=2 -mvscale-max=2 -O2 -emit-llvm %s -o - \
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// RUN: | FileCheck %s
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// Test RISC-V V-extension fixed-length vector inline assembly constraints.
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#include <riscv_vector.h>
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#include <stdbool.h>
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typedef vbool1_t fixed_bool1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vint32m1_t fixed_i32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vint8mf2_t fixed_i8mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen / 2)));
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typedef bool bx2 __attribute__((ext_vector_type(16)));
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typedef int i32x2 __attribute__((ext_vector_type(2)));
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typedef char i8x4 __attribute__((ext_vector_type(4)));
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fixed_i32m1_t test_vr(fixed_i32m1_t a) {
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// CHECK-LABEL: define{{.*}} @test_vr
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// CHECK: %0 = tail call <4 x i32> asm sideeffect "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<4 x i32> %a, <4 x i32> %a)
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fixed_i32m1_t ret;
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asm volatile ("vadd.vv %0, %1, %2" : "=vr"(ret) : "vr"(a), "vr"(a));
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return ret;
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}
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i32x2 test_vr2(i32x2 a) {
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// CHECK-LABEL: define{{.*}} @test_vr2
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// CHECK: %1 = tail call <2 x i32> asm sideeffect "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<2 x i32> %0, <2 x i32> %0)
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i32x2 ret;
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asm volatile ("vadd.vv %0, %1, %2" : "=vr"(ret) : "vr"(a), "vr"(a));
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return ret;
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}
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fixed_i8mf2_t test_vd(fixed_i8mf2_t a) {
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// CHECK-LABEL: define{{.*}} @test_vd
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// CHECK: %0 = tail call <8 x i8> asm sideeffect "vadd.vv $0, $1, $2", "=^vd,^vr,^vr"(<8 x i8> %a, <8 x i8> %a)
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fixed_i8mf2_t ret;
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asm volatile ("vadd.vv %0, %1, %2" : "=vd"(ret) : "vr"(a), "vr"(a));
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return ret;
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}
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i8x4 test_vd2(i8x4 a) {
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// CHECK-LABEL: define{{.*}} @test_vd2
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// CHECK: %1 = tail call <4 x i8> asm sideeffect "vadd.vv $0, $1, $2", "=^vd,^vr,^vr"(<4 x i8> %0, <4 x i8> %0)
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i8x4 ret;
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asm volatile ("vadd.vv %0, %1, %2" : "=vd"(ret) : "vr"(a), "vr"(a));
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return ret;
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}
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fixed_bool1_t test_vm(fixed_bool1_t a) {
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// CHECK-LABEL: define{{.*}} @test_vm
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// CHECK: %1 = tail call <16 x i8> asm sideeffect "vmand.mm $0, $1, $2", "=^vm,^vm,^vm"(<16 x i8> %a, <16 x i8> %a)
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fixed_bool1_t ret;
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asm volatile ("vmand.mm %0, %1, %2" : "=vm"(ret) : "vm"(a), "vm"(a));
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return ret;
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}
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void test_vm2(bx2 a) {
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// CHECK-LABEL: define{{.*}} @test_vm2
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// CHECK: tail call void asm sideeffect "dummy $0", "^vm"(<16 x i1> %a1)
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asm volatile ("dummy %0" :: "vm"(a));
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}

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 36 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -23408,6 +23408,12 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2340823408
&RISCV::VRN2M4RegClass}) {
2340923409
if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy))
2341023410
return std::make_pair(0U, RC);
23411+
23412+
if (VT.isFixedLengthVector() && useRVVForFixedLengthVectorVT(VT)) {
23413+
MVT ContainerVT = getContainerForFixedLengthVector(VT);
23414+
if (TRI->isTypeLegalForClass(*RC, ContainerVT))
23415+
return std::make_pair(0U, RC);
23416+
}
2341123417
}
2341223418
} else if (Constraint == "vd") {
2341323419
for (const auto *RC :
@@ -23421,10 +23427,24 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2342123427
&RISCV::VRN2M4NoV0RegClass}) {
2342223428
if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy))
2342323429
return std::make_pair(0U, RC);
23430+
23431+
if (VT.isFixedLengthVector() && useRVVForFixedLengthVectorVT(VT)) {
23432+
MVT ContainerVT = getContainerForFixedLengthVector(VT);
23433+
if (TRI->isTypeLegalForClass(*RC, ContainerVT))
23434+
return std::make_pair(0U, RC);
23435+
}
2342423436
}
2342523437
} else if (Constraint == "vm") {
2342623438
if (TRI->isTypeLegalForClass(RISCV::VMV0RegClass, VT.SimpleTy))
2342723439
return std::make_pair(0U, &RISCV::VMV0RegClass);
23440+
23441+
if (VT.isFixedLengthVector() && useRVVForFixedLengthVectorVT(VT)) {
23442+
MVT ContainerVT = getContainerForFixedLengthVector(VT);
23443+
// VT here might be coerced to vector with i8 elements, so we need to
23444+
// check if this is a M1 register here instead of checking VMV0RegClass.
23445+
if (TRI->isTypeLegalForClass(RISCV::VRRegClass, ContainerVT))
23446+
return std::make_pair(0U, &RISCV::VMV0RegClass);
23447+
}
2342823448
} else if (Constraint == "cr") {
2342923449
if (VT == MVT::f16 && Subtarget.hasStdExtZhinxmin())
2343023450
return std::make_pair(0U, &RISCV::GPRF16CRegClass);
@@ -24302,7 +24322,12 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
2430224322
return true;
2430324323
}
2430424324

24305-
if (ValueVT.isScalableVector() && PartVT.isScalableVector()) {
24325+
if ((ValueVT.isScalableVector() || ValueVT.isFixedLengthVector()) &&
24326+
PartVT.isScalableVector()) {
24327+
if (ValueVT.isFixedLengthVector()) {
24328+
ValueVT = getContainerForFixedLengthVector(ValueVT.getSimpleVT());
24329+
Val = convertToScalableVector(ValueVT, Val, DAG, Subtarget);
24330+
}
2430624331
LLVMContext &Context = *DAG.getContext();
2430724332
EVT ValueEltVT = ValueVT.getVectorElementType();
2430824333
EVT PartEltVT = PartVT.getVectorElementType();
@@ -24372,12 +24397,17 @@ SDValue RISCVTargetLowering::joinRegisterPartsIntoValue(
2437224397
return Val;
2437324398
}
2437424399

24375-
if (ValueVT.isScalableVector() && PartVT.isScalableVector()) {
24400+
if ((ValueVT.isScalableVector() || ValueVT.isFixedLengthVector()) &&
24401+
PartVT.isScalableVector()) {
2437624402
LLVMContext &Context = *DAG.getContext();
2437724403
SDValue Val = Parts[0];
2437824404
EVT ValueEltVT = ValueVT.getVectorElementType();
2437924405
EVT PartEltVT = PartVT.getVectorElementType();
2438024406
unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinValue();
24407+
if (ValueVT.isFixedLengthVector())
24408+
ValueVTBitSize = getContainerForFixedLengthVector(ValueVT.getSimpleVT())
24409+
.getSizeInBits()
24410+
.getKnownMinValue();
2438124411
unsigned PartVTBitSize = PartVT.getSizeInBits().getKnownMinValue();
2438224412
if (PartVTBitSize % ValueVTBitSize == 0) {
2438324413
assert(PartVTBitSize >= ValueVTBitSize);
@@ -24395,7 +24425,10 @@ SDValue RISCVTargetLowering::joinRegisterPartsIntoValue(
2439524425
EVT::getVectorVT(Context, ValueEltVT, Count, /*IsScalable=*/true);
2439624426
Val = DAG.getNode(ISD::BITCAST, DL, SameEltTypeVT, Val);
2439724427
}
24398-
Val = DAG.getExtractSubvector(DL, ValueVT, Val, 0);
24428+
if (ValueVT.isFixedLengthVector())
24429+
Val = convertFromScalableVector(ValueVT, Val, DAG, Subtarget);
24430+
else
24431+
Val = DAG.getExtractSubvector(DL, ValueVT, Val, 0);
2439924432
return Val;
2440024433
}
2440124434
}

‎llvm/test/CodeGen/RISCV/inline-asm-fixed-v-constraint.ll

Lines changed: 68 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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define <1 x i8> @constraint_vr_fixed(<1 x i8> %0, <1 x i8> %1) nounwind {
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; RV32I-LABEL: constraint_vr_fixed:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: vadd.vv v8, v8, v9
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_vr_fixed:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: vadd.vv v8, v8, v9
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%a = tail call <1 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(
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<1 x i8> %0, <1 x i8> %1)
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ret <1 x i8> %a
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}
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define <4 x i32> @constraint_vd_fixed(<4 x i32> %0, <4 x i32> %1) nounwind {
27+
; RV32I-LABEL: constraint_vd_fixed:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: vadd.vv v8, v8, v9
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_vd_fixed:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: vadd.vv v8, v8, v9
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%a = tail call <4 x i32> asm "vadd.vv $0, $1, $2", "=^vd,^vr,^vr"(
41+
<4 x i32> %0, <4 x i32> %1)
42+
ret <4 x i32> %a
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}
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define <16 x i1> @constraint_vm_fixed(<16 x i1> %0, <16 x i1> %1) nounwind {
46+
; RV32I-LABEL: constraint_vm_fixed:
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; RV32I: # %bb.0:
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; RV32I-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV32I-NEXT: vmv1r.v v9, v0
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; RV32I-NEXT: vmv1r.v v0, v8
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; RV32I-NEXT: #APP
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; RV32I-NEXT: vadd.vv v0, v9, v0
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_vm_fixed:
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; RV64I: # %bb.0:
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; RV64I-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV64I-NEXT: vmv1r.v v9, v0
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; RV64I-NEXT: vmv1r.v v0, v8
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; RV64I-NEXT: #APP
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; RV64I-NEXT: vadd.vv v0, v9, v0
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
65+
%a = tail call <16 x i1> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vm"(
66+
<16 x i1> %0, <16 x i1> %1)
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ret <16 x i1> %a
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}

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