Remove unnecessary functions for getting PR operation action

Author: JamesChesterman

llvm/include/llvm/CodeGen/TargetLowering.h

@@ -1639,25 +1639,6 @@ class TargetLoweringBase {
            getCondCodeAction(CC, VT) == Custom;
   }
 
-  /// Return how a PARTIAL_REDUCE_U/SMLA node with Acc type AccVT and Input type
-  /// InputVT should be treated. Either it's legal, needs to be promoted to a
-  /// larger size, needs to be expanded to some other code sequence, or the
-  /// target has a custom expander for it.
-  LegalizeAction getPartialReduceMLAAction(EVT AccVT, EVT InputVT) const {
-    unsigned AccI = (unsigned)AccVT.getSimpleVT().SimpleTy;
-    unsigned InputI = (unsigned)InputVT.getSimpleVT().SimpleTy;
-    assert(AccI < MVT::VALUETYPE_SIZE && InputI < MVT::VALUETYPE_SIZE &&
-           "Table isn't big enough!");
-    return PartialReduceMLAActions[AccI][InputI];
-  }
-
-  /// Return true if a PARTIAL_REDUCE_U/SMLA node with the specified types is
-  /// legal or custom for this target.
-  bool isPartialReduceMLALegalOrCustom(EVT AccVT, EVT InputVT) const {
-    return getPartialReduceMLAAction(AccVT, InputVT) == Legal ||
-           getPartialReduceMLAAction(AccVT, InputVT) == Custom;
-  }
-
   /// If the action for this operation is to promote, this method returns the
   /// ValueType to promote to.
   MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
@@ -2723,16 +2704,6 @@ class TargetLoweringBase {
       setCondCodeAction(CCs, VT, Action);
   }
 
-  /// Indicate how a PARTIAL_REDUCE_U/SMLA node with Acc type AccVT and Input
-  /// type InputVT should be treated by the target. Either it's legal, needs to
-  /// be promoted to a larger size, needs to be expanded to some other code
-  /// sequence, or the target has a custom expander for it.
-  void setPartialReduceMLAAction(MVT AccVT, MVT InputVT,
-                                 LegalizeAction Action) {
-    assert(AccVT.isValid() && InputVT.isValid() && "Table isn't big enough!");
-    PartialReduceMLAActions[AccVT.SimpleTy][InputVT.SimpleTy] = Action;
-  }
-
   /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
   /// to trying a larger integer/fp until it can find one that works. If that
   /// default is insufficient, this method can be used by the target to override
@@ -3679,12 +3650,6 @@ class TargetLoweringBase {
   /// up the MVT::VALUETYPE_SIZE value to the next multiple of 8.
   uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::VALUETYPE_SIZE + 7) / 8];
 
-  /// For each result type and input type for the ISD::PARTIAL_REDUCE_U/SMLA
-  /// nodes, keep a LegalizeAction which indicates how instruction selection
-  /// should deal with this operation.
-  LegalizeAction PartialReduceMLAActions[MVT::VALUETYPE_SIZE]
-                                        [MVT::VALUETYPE_SIZE];
-
   ValueTypeActionImpl ValueTypeActions;
 
 private:

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -622,8 +622,6 @@ namespace {
     SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
     SDValue foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG,
                                  const TargetLowering &TLI);
-    SDValue foldMulPARTIAL_REDUCE_MLA(SDNode *N);
-    SDValue foldExtendPARTIAL_REDUCE_MLA(SDNode *N);
 
     SDValue CombineExtLoad(SDNode *N);
     SDValue CombineZExtLogicopShiftLoad(SDNode *N);

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

@@ -469,6 +469,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
   case ISD::VECTOR_COMPRESS:
   case ISD::SCMP:
   case ISD::UCMP:
+  case ISD::PARTIAL_REDUCE_UMLA:
+  case ISD::PARTIAL_REDUCE_SMLA:
     Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
     break;
   case ISD::SMULFIX:
@@ -522,11 +524,6 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
       Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
     break;
   }
-  case ISD::PARTIAL_REDUCE_UMLA:
-  case ISD::PARTIAL_REDUCE_SMLA:
-    Action = TLI.getPartialReduceMLAAction(Node->getValueType(0),
-                                           Node->getOperand(1).getValueType());
-    break;
 
 #define BEGIN_REGISTER_VP_SDNODE(VPID, LEGALPOS, ...)                          \
   case ISD::VPID: {                                                            \

llvm/lib/CodeGen/TargetLoweringBase.cpp

@@ -836,8 +836,9 @@ void TargetLoweringBase::initActions() {
     setOperationAction(ISD::SET_FPENV, VT, Expand);
     setOperationAction(ISD::RESET_FPENV, VT, Expand);
 
-    for (MVT InputVT : MVT::all_valuetypes())
-      setPartialReduceMLAAction(VT, InputVT, Expand);
+    // PartialReduceMLA operations default to expand.
+    setOperationAction({ISD::PARTIAL_REDUCE_UMLA, ISD::PARTIAL_REDUCE_SMLA}, VT,
+                       Expand);
   }
 
   // Most targets ignore the @llvm.prefetch intrinsic.