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[llvm][CodeGen] avoid repeated interval calculation in window scheduler
Some new registers may be reused when replacing some old ones in certain use case of ModuloScheduleExpander. It is necessary to avoid repeated interval calculations for these registers.
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3 files changed

+110
-6
lines changed

3 files changed

+110
-6
lines changed

‎llvm/include/llvm/CodeGen/ModuloSchedule.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,7 @@
6060
#ifndef LLVM_CODEGEN_MODULOSCHEDULE_H
6161
#define LLVM_CODEGEN_MODULOSCHEDULE_H
6262

63+
#include "llvm/ADT/SmallSet.h"
6364
#include "llvm/CodeGen/MachineFunction.h"
6465
#include "llvm/CodeGen/MachineLoopUtils.h"
6566
#include "llvm/CodeGen/TargetInstrInfo.h"
@@ -189,7 +190,7 @@ class ModuloScheduleExpander {
189190
InstrChangesTy InstrChanges;
190191

191192
/// Record the registers that need to compute live intervals.
192-
SmallVector<Register> NoIntervalRegs;
193+
SmallSet<Register, 8> NoIntervalRegs;
193194

194195
void generatePipelinedLoop();
195196
void generateProlog(unsigned LastStage, MachineBasicBlock *KernelBB,

‎llvm/lib/CodeGen/ModuloSchedule.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -551,7 +551,7 @@ void ModuloScheduleExpander::generateExistingPhis(
551551

552552
if (IsLast && np == NumPhis - 1) {
553553
replaceRegUsesAfterLoop(Def, NewReg, BB, MRI);
554-
NoIntervalRegs.push_back(NewReg);
554+
NoIntervalRegs.insert(NewReg);
555555
}
556556
continue;
557557
}
@@ -594,7 +594,7 @@ void ModuloScheduleExpander::generateExistingPhis(
594594
// epilog.
595595
if (IsLast && np == NumPhis - 1) {
596596
replaceRegUsesAfterLoop(Def, NewReg, BB, MRI);
597-
NoIntervalRegs.push_back(NewReg);
597+
NoIntervalRegs.insert(NewReg);
598598
}
599599

600600
// In the kernel, a dependent Phi uses the value from this Phi.
@@ -617,7 +617,7 @@ void ModuloScheduleExpander::generateExistingPhis(
617617
auto It = CurStageMap.find(LoopVal);
618618
if (It != CurStageMap.end()) {
619619
replaceRegUsesAfterLoop(Def, It->second, BB, MRI);
620-
NoIntervalRegs.push_back(It->second);
620+
NoIntervalRegs.insert(It->second);
621621
}
622622
}
623623
}
@@ -740,7 +740,7 @@ void ModuloScheduleExpander::generatePhis(
740740
}
741741
if (IsLast && np == NumPhis - 1) {
742742
replaceRegUsesAfterLoop(Def, NewReg, BB, MRI);
743-
NoIntervalRegs.push_back(NewReg);
743+
NoIntervalRegs.insert(NewReg);
744744
}
745745
}
746746
}
@@ -1083,7 +1083,7 @@ void ModuloScheduleExpander::updateInstruction(MachineInstr *NewMI,
10831083
VRMap[CurStageNum][reg] = NewReg;
10841084
if (LastDef) {
10851085
replaceRegUsesAfterLoop(reg, NewReg, BB, MRI);
1086-
NoIntervalRegs.push_back(NewReg);
1086+
NoIntervalRegs.insert(NewReg);
10871087
}
10881088
} else if (MO.isUse()) {
10891089
MachineInstr *Def = MRI.getVRegDef(reg);

‎llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir‎

Lines changed: 103 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,103 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc --mtriple=aarch64 %s -O2 -run-pass=pipeliner -o - | FileCheck %s
3+
4+
...
5+
---
6+
name: foo
7+
tracksRegLiveness: true
8+
body: |
9+
; CHECK-LABEL: name: foo
10+
; CHECK: bb.0:
11+
; CHECK-NEXT: successors: %bb.3(0x80000000)
12+
; CHECK-NEXT: liveins: $x0
13+
; CHECK-NEXT: {{ $}}
14+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
15+
; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
16+
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
17+
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
18+
; CHECK-NEXT: {{ $}}
19+
; CHECK-NEXT: bb.3:
20+
; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.7(0x40000000)
21+
; CHECK-NEXT: {{ $}}
22+
; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[FMOVD0_]], [[FMOVD0_]], implicit $fpcr
23+
; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = nsw SUBSXri [[SUBREG_TO_REG]], 1, 0, implicit-def $nzcv
24+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[SUBSXri]]
25+
; CHECK-NEXT: [[FMOVDi:%[0-9]+]]:fpr64 = FMOVDi 112
26+
; CHECK-NEXT: Bcc 0, %bb.7, implicit $nzcv
27+
; CHECK-NEXT: B %bb.4
28+
; CHECK-NEXT: {{ $}}
29+
; CHECK-NEXT: bb.4:
30+
; CHECK-NEXT: successors: %bb.5(0x80000000), %bb.6(0x00000000)
31+
; CHECK-NEXT: {{ $}}
32+
; CHECK-NEXT: [[FADDDrr1:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[FADDDrr]], [[FMOVD0_]], implicit $fpcr
33+
; CHECK-NEXT: [[FADDDrr2:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[FMOVD0_]], [[FMOVD0_]], implicit $fpcr
34+
; CHECK-NEXT: [[SUBSXri1:%[0-9]+]]:gpr64 = nsw SUBSXri [[COPY1]], 1, 0, implicit-def $nzcv
35+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[SUBSXri1]]
36+
; CHECK-NEXT: [[FMOVDi1:%[0-9]+]]:fpr64 = FMOVDi 112
37+
; CHECK-NEXT: Bcc 0, %bb.6, implicit $nzcv
38+
; CHECK-NEXT: B %bb.5
39+
; CHECK-NEXT: {{ $}}
40+
; CHECK-NEXT: bb.5:
41+
; CHECK-NEXT: successors: %bb.6(0x04000000), %bb.5(0x7c000000)
42+
; CHECK-NEXT: {{ $}}
43+
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr64sp = PHI [[COPY2]], %bb.4, %24, %bb.5
44+
; CHECK-NEXT: [[PHI1:%[0-9]+]]:fpr64 = PHI [[FMOVDi1]], %bb.4, %25, %bb.5
45+
; CHECK-NEXT: [[PHI2:%[0-9]+]]:fpr64 = PHI [[FMOVDi]], %bb.4, [[PHI1]], %bb.5
46+
; CHECK-NEXT: [[PHI3:%[0-9]+]]:fpr64 = PHI [[FADDDrr2]], %bb.4, %22, %bb.5
47+
; CHECK-NEXT: [[PHI4:%[0-9]+]]:fpr64 = PHI [[FADDDrr1]], %bb.4, %23, %bb.5
48+
; CHECK-NEXT: [[SUBSXri2:%[0-9]+]]:gpr64 = nsw SUBSXri [[PHI]], 1, 0, implicit-def $nzcv
49+
; CHECK-NEXT: [[FADDDrr3:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[PHI2]], [[FMOVD0_]], implicit $fpcr
50+
; CHECK-NEXT: [[FADDDrr4:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[PHI3]], [[PHI2]], implicit $fpcr
51+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64all = COPY [[SUBSXri2]]
52+
; CHECK-NEXT: STRDui [[PHI4]], [[COPY]], 0
53+
; CHECK-NEXT: [[FMOVDi2:%[0-9]+]]:fpr64 = FMOVDi 112
54+
; CHECK-NEXT: Bcc 1, %bb.5, implicit $nzcv
55+
; CHECK-NEXT: B %bb.6
56+
; CHECK-NEXT: {{ $}}
57+
; CHECK-NEXT: bb.6:
58+
; CHECK-NEXT: successors: %bb.7(0x80000000)
59+
; CHECK-NEXT: {{ $}}
60+
; CHECK-NEXT: [[PHI5:%[0-9]+]]:fpr64 = PHI [[FMOVDi]], %bb.4, [[PHI1]], %bb.5
61+
; CHECK-NEXT: [[PHI6:%[0-9]+]]:fpr64 = PHI [[FADDDrr2]], %bb.4, [[FADDDrr3]], %bb.5
62+
; CHECK-NEXT: [[PHI7:%[0-9]+]]:fpr64 = PHI [[FADDDrr1]], %bb.4, [[FADDDrr4]], %bb.5
63+
; CHECK-NEXT: STRDui [[PHI7]], [[COPY]], 0
64+
; CHECK-NEXT: {{ $}}
65+
; CHECK-NEXT: bb.7:
66+
; CHECK-NEXT: successors: %bb.2(0x80000000)
67+
; CHECK-NEXT: {{ $}}
68+
; CHECK-NEXT: [[PHI8:%[0-9]+]]:fpr64 = PHI [[FMOVD0_]], %bb.3, [[PHI5]], %bb.6
69+
; CHECK-NEXT: [[PHI9:%[0-9]+]]:fpr64 = PHI [[FADDDrr]], %bb.3, [[PHI6]], %bb.6
70+
; CHECK-NEXT: [[FADDDrr5:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[PHI9]], [[PHI8]], implicit $fpcr
71+
; CHECK-NEXT: STRDui [[FADDDrr5]], [[COPY]], 0
72+
; CHECK-NEXT: B %bb.2
73+
; CHECK-NEXT: {{ $}}
74+
; CHECK-NEXT: bb.2:
75+
; CHECK-NEXT: RET_ReallyLR
76+
bb.0:
77+
successors: %bb.1(0x80000000)
78+
liveins: $x0
79+
80+
%0:gpr64common = COPY $x0
81+
%1:fpr64 = FMOVD0
82+
%2:gpr32 = MOVi32imm 1
83+
%3:gpr64all = SUBREG_TO_REG 0, killed %2, %subreg.sub_32
84+
85+
bb.1:
86+
successors: %bb.2(0x04000000), %bb.1(0x7c000000)
87+
88+
%4:gpr64sp = PHI %3, %bb.0, %5, %bb.1
89+
%6:fpr64 = PHI %1, %bb.0, %7, %bb.1
90+
%8:fpr64 = PHI %1, %bb.0, %6, %bb.1
91+
%9:fpr64 = nofpexcept FADDDrr %8, %1, implicit $fpcr
92+
%10:fpr64 = nofpexcept FADDDrr killed %9, %6, implicit $fpcr
93+
STRDui killed %10, %0, 0
94+
%11:gpr64 = nsw SUBSXri %4, 1, 0, implicit-def $nzcv
95+
%5:gpr64all = COPY %11
96+
%7:fpr64 = FMOVDi 112
97+
Bcc 1, %bb.1, implicit $nzcv
98+
B %bb.2
99+
100+
bb.2:
101+
RET_ReallyLR
102+
103+
...

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