fixup! [RISCV] Xqciint SystemRegs, Final Assembly Insts

Author: lenary

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

@@ -126,9 +126,9 @@ static const MCPhysReg FixedCSRFIMap[] = {
 static constexpr uint64_t QCIInterruptPushAmount = 96;
 
 static const std::pair<MCPhysReg, int8_t> FixedCSRFIQCIInterruptMap[] = {
-    /* -1 is a gap for mepc/qc.mnepc */
+    /* -1 is a gap for mepc/mnepc */
     {/*fp*/ FPReg, -2},
-    /* -3 is a gap for mcause */
+    /* -3 is a gap for qc.mcause */
     {/*ra*/ RAReg, -4},
     /* -5 is reserved */
     {/*t0*/ RISCV::X5, -6},

llvm/lib/Target/RISCV/RISCVSystemOperands.td

@@ -479,8 +479,6 @@ def : SysReg<"mctrctl", 0x34e>;
 // Xqciint
 let FeaturesRequired = [{ {RISCV::FeatureVendorXqciint} }], isRV32Only = 1 in {
 def : SysReg<"qc.mmcr", 0x7C0>;
-def : SysReg<"qc.mnepc", 0x7C1>;
-def : SysReg<"qc.mncause", 0x7C2>;
 def : SysReg<"qc.mntvec", 0x7C3>;
 def : SysReg<"qc.mstktopaddr", 0x7C4>;
 def : SysReg<"qc.mstkbottomaddr", 0x7C5>;

llvm/test/MC/RISCV/xqciint-csrs-invalid.s

@@ -5,12 +5,6 @@
 csrrs t2, qc.mmcr, zero
 // CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mmcr' requires 'experimental-xqciint' to be enabled
 
-csrrs t2, qc.mnepc, zero
-// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mnepc' requires 'experimental-xqciint' to be enabled
-
-csrrs t2, qc.mncause, zero
-// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mncause' requires 'experimental-xqciint' to be enabled
-
 csrrs t2, qc.mntvec, zero
 // CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mntvec' requires 'experimental-xqciint' to be enabled
 

llvm/test/MC/RISCV/xqciint-csrs-valid.s

@@ -12,20 +12,6 @@ csrrs t2, 0x7C0, zero
 // CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c]
 // CHECK-INST: csrrs t2, qc.mmcr, zero
 
-csrrs t2, qc.mnepc, zero
-// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
-// CHECK-INST: csrrs    t2, qc.mnepc, zero
-csrrs t2, 0x7C1, zero
-// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
-// CHECK-INST: csrrs    t2, qc.mnepc, zero
-
-csrrs t2, qc.mncause, zero
-// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7c]
-// CHECK-INST: csrrs    t2, qc.mncause, zero
-csrrs t2, 0x7C2, zero
-// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7c]
-// CHECK-INST: csrrs    t2, qc.mncause, zero
-
 csrrs t2, qc.mntvec, zero
 // CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7c]
 // CHECK-INST: csrrs    t2, qc.mntvec, zero