[M68k] add 32 bit branch instrs and allow x20 and later CPUs to relax to 32 bit versions

Author: knickish

llvm/lib/Target/M68k/M68kInstrControl.td

@@ -190,6 +190,12 @@ foreach cc = [ "cc", "ls", "lt", "eq", "mi", "ne", "ge",
   def B#cc#"16"
     : MxBcc<cc, MxBrTarget16, (descend 0b0000, 0b0000),
             (operand "$dst", 16, (encoder "encodePCRelImm<16>"))>;
+
+  let Predicates = [AtLeastM68020] in {
+  def B#cc#"32"
+    : MxBcc<cc, MxBrTarget32, (descend 0b1111, 0b1111),
+            (operand "$dst", 16, (encoder "encodePCRelImm<32>"))>;
+  } // AtLeastM68020
 }
 
 foreach cc = [ "cc", "ls", "lt", "eq", "mi", "ne", "ge",
@@ -223,6 +229,12 @@ def BRA8  : MxBra<MxBrTarget8,
 def BRA16 : MxBra<MxBrTarget16, (descend 0b0000, 0b0000),
                   (operand "$dst", 16, (encoder "encodePCRelImm<16>"))>;
 
+let Predicates = [AtLeastM68020] in {
+def BRA32 : MxBra<MxBrTarget16, (descend 0b1111, 0b1111),
+                  (operand "$dst", 32, (encoder "encodePCRelImm<32>"),
+                                       (decoder "DecodeImm32"))>;
+} // AtLeastM68020
+
 def : Pat<(br bb:$target), (BRA8 MxBrTarget8:$target)>;
 
 /// -------------------------------------------------
@@ -250,9 +262,11 @@ def BSR8 : MxBsr<MxBrTarget8, MxType8,
 def BSR16 : MxBsr<MxBrTarget16, MxType16, (descend 0b0000, 0b0000),
                 (operand "$dst", 16, (encoder "encodePCRelImm<16>"))>;
 
+let Predicates = [AtLeastM68020] in {
 def BSR32 : MxBsr<MxBrTarget32, MxType32, (descend 0b1111, 0b1111),
                 (operand "$dst", 32, (encoder "encodePCRelImm<32>"),
                                      (decoder "DecodeImm32"))>;
+} // AtLeastM68020
 
 //===----------------------------------------------------------------------===//
 // Call

llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp

@@ -39,9 +39,14 @@ using namespace llvm;
 namespace {
 
 class M68kAsmBackend : public MCAsmBackend {
+  bool Allows32BitBranch;
 
 public:
-  M68kAsmBackend(const Target &T) : MCAsmBackend(llvm::endianness::big) {}
+  M68kAsmBackend(const Target &T, const MCSubtargetInfo &STI)
+      : MCAsmBackend(llvm::endianness::big),
+        Allows32BitBranch(llvm::StringSwitch<bool>(STI.getCPU())
+                              .CasesLower("m68020", "m68030", "m68040", true)
+                              .Default(false)) {}
 
   unsigned getNumFixupKinds() const override { return 0; }
 
@@ -129,6 +134,36 @@ static unsigned getRelaxedOpcodeBranch(const MCInst &Inst) {
     return M68k::Ble16;
   case M68k::Bvs8:
     return M68k::Bvs16;
+  case M68k::BRA16:
+    return M68k::BRA32;
+  case M68k::Bcc16:
+    return M68k::Bcc32;
+  case M68k::Bls16:
+    return M68k::Bls32;
+  case M68k::Blt16:
+    return M68k::Blt32;
+  case M68k::Beq16:
+    return M68k::Beq32;
+  case M68k::Bmi16:
+    return M68k::Bmi32;
+  case M68k::Bne16:
+    return M68k::Bne32;
+  case M68k::Bge16:
+    return M68k::Bge32;
+  case M68k::Bcs16:
+    return M68k::Bcs32;
+  case M68k::Bpl16:
+    return M68k::Bpl32;
+  case M68k::Bgt16:
+    return M68k::Bgt32;
+  case M68k::Bhi16:
+    return M68k::Bhi32;
+  case M68k::Bvc16:
+    return M68k::Bvc32;
+  case M68k::Ble16:
+    return M68k::Ble32;
+  case M68k::Bvs16:
+    return M68k::Bvs32;
   }
 }
 
@@ -168,7 +203,7 @@ bool M68kAsmBackend::mayNeedRelaxation(const MCInst &Inst,
 bool M68kAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
                                           uint64_t Value) const {
   // TODO Newer CPU can use 32 bit offsets, so check for this when ready
-  if (!isInt<16>(Value)) {
+  if (!isInt<32>(Value) || (!Allows32BitBranch && !isInt<16>(Value))) {
     llvm_unreachable("Cannot relax the instruction, value does not fit");
   }
   // Relax if the value is too big for a (signed) i8. This means that byte-wide
@@ -178,7 +213,13 @@ bool M68kAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
   // A branch to the immediately following instruction automatically
   // uses the 16-bit displacement format because the 8-bit
   // displacement field contains $00 (zero offset).
-  return Value == 0 || !isInt<8>(Value);
+  unsigned int KindLog2Size = getFixupKindLog2Size(Fixup.getKind());
+  bool FixupFieldTooSmall = false;
+  if (!isInt<8>(Value) && KindLog2Size == 0)
+    FixupFieldTooSmall |= true;
+  if (!isInt<16>(Value) && KindLog2Size <= 1)
+    FixupFieldTooSmall |= true;
+  return Value == 0 || FixupFieldTooSmall;
 }
 
 // NOTE Can tblgen help at all here to verify there aren't other instructions
@@ -218,8 +259,8 @@ namespace {
 class M68kELFAsmBackend : public M68kAsmBackend {
 public:
   uint8_t OSABI;
-  M68kELFAsmBackend(const Target &T, uint8_t OSABI)
-      : M68kAsmBackend(T), OSABI(OSABI) {}
+  M68kELFAsmBackend(const Target &T, const MCSubtargetInfo &STI, uint8_t OSABI)
+      : M68kAsmBackend(T, STI), OSABI(OSABI) {}
 
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
@@ -235,5 +276,5 @@ MCAsmBackend *llvm::createM68kAsmBackend(const Target &T,
                                          const MCTargetOptions &Options) {
   const Triple &TheTriple = STI.getTargetTriple();
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
-  return new M68kELFAsmBackend(T, OSABI);
+  return new M68kELFAsmBackend(T, STI, OSABI);
 }

llvm/test/MC/M68k/Relaxations/branch32.s

@@ -0,0 +1,11 @@
+; RUN: llvm-mc -triple=m68k --mcpu=m68020 -motorola-integers -filetype=obj < %s \
+; RUN:     | llvm-objdump -d - | FileCheck %s
+
+; CHECK-LABEL: <RELAXED_32>:
+RELAXED_32:
+	; CHECK: bra  $ff
+	bra	.LBB3_1
+	.space 0x20000  ; Greater than u16::MAX.
+.LBB3_1:
+	add.l	#0, %d0
+	rts