Skip to content

Commit 99a6f75

Browse files
iajbariajbar
committed
[Hexagon] Add V81 instructions and intrinsics
1 parent 855a3e9 commit 99a6f75

File tree

5 files changed

+1159
-0
lines changed

5 files changed

+1159
-0
lines changed

‎clang/lib/Headers/hvx_hexagon_protos.h‎

Lines changed: 341 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5605,6 +5605,347 @@
56055605
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_f8)(Vu, Vv)
56065606
#endif /* __HEXAGON_ARCH___ >= 79 */
56075607

5608+
#if __HVX_ARCH__ >= 81
5609+
/* ==========================================================================
5610+
Assembly Syntax: Vd32.qf16=vabs(Vu32.hf)
5611+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vhf(HVX_Vector Vu)
5612+
Instruction Type: CVI_VS
5613+
Execution Slots: SLOT0123
5614+
========================================================================== */
5615+
5616+
#define Q6_Vqf16_vabs_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_hf)(Vu)
5617+
#endif /* __HEXAGON_ARCH___ >= 81 */
5618+
5619+
#if __HVX_ARCH__ >= 81
5620+
/* ==========================================================================
5621+
Assembly Syntax: Vd32.qf16=vabs(Vu32.qf16)
5622+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vqf16(HVX_Vector Vu)
5623+
Instruction Type: CVI_VS
5624+
Execution Slots: SLOT0123
5625+
========================================================================== */
5626+
5627+
#define Q6_Vqf16_vabs_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_qf16)(Vu)
5628+
#endif /* __HEXAGON_ARCH___ >= 81 */
5629+
5630+
#if __HVX_ARCH__ >= 81
5631+
/* ==========================================================================
5632+
Assembly Syntax: Vd32.qf32=vabs(Vu32.qf32)
5633+
C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vqf32(HVX_Vector Vu)
5634+
Instruction Type: CVI_VS
5635+
Execution Slots: SLOT0123
5636+
========================================================================== */
5637+
5638+
#define Q6_Vqf32_vabs_Vqf32(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_qf32)(Vu)
5639+
#endif /* __HEXAGON_ARCH___ >= 81 */
5640+
5641+
#if __HVX_ARCH__ >= 81
5642+
/* ==========================================================================
5643+
Assembly Syntax: Vd32.qf32=vabs(Vu32.sf)
5644+
C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vsf(HVX_Vector Vu)
5645+
Instruction Type: CVI_VS
5646+
Execution Slots: SLOT0123
5647+
========================================================================== */
5648+
5649+
#define Q6_Vqf32_vabs_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_sf)(Vu)
5650+
#endif /* __HEXAGON_ARCH___ >= 81 */
5651+
5652+
#if __HVX_ARCH__ >= 81
5653+
/* ==========================================================================
5654+
Assembly Syntax: Vd32=valign4(Vu32,Vv32,Rt8)
5655+
C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
5656+
Instruction Type: CVI_VA
5657+
Execution Slots: SLOT0123
5658+
========================================================================== */
5659+
5660+
#define Q6_V_valign4_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valign4)(Vu,Vv,Rt)
5661+
#endif /* __HEXAGON_ARCH___ >= 81 */
5662+
5663+
#if __HVX_ARCH__ >= 81
5664+
/* ==========================================================================
5665+
Assembly Syntax: Vd32.bf=Vuu32.qf32
5666+
C Intrinsic Prototype: HVX_Vector Q6_Vbf_equals_Wqf32(HVX_VectorPair Vuu)
5667+
Instruction Type: CVI_VS
5668+
Execution Slots: SLOT0123
5669+
========================================================================== */
5670+
5671+
#define Q6_Vbf_equals_Wqf32(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_bf_qf32)(Vuu)
5672+
#endif /* __HEXAGON_ARCH___ >= 81 */
5673+
5674+
#if __HVX_ARCH__ >= 81
5675+
/* ==========================================================================
5676+
Assembly Syntax: Vd32.f8=Vu32.qf16
5677+
C Intrinsic Prototype: HVX_Vector Q6_V_equals_Vqf16(HVX_Vector Vu)
5678+
Instruction Type: CVI_VS
5679+
Execution Slots: SLOT0123
5680+
========================================================================== */
5681+
5682+
#define Q6_V_equals_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_f8_qf16)(Vu)
5683+
#endif /* __HEXAGON_ARCH___ >= 81 */
5684+
5685+
#if __HVX_ARCH__ >= 81
5686+
/* ==========================================================================
5687+
Assembly Syntax: Vd32.h=Vu32.hf:rnd
5688+
C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf_rnd(HVX_Vector Vu)
5689+
Instruction Type: CVI_VS
5690+
Execution Slots: SLOT0123
5691+
========================================================================== */
5692+
5693+
#define Q6_Vh_equals_Vhf_rnd(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf_rnd)(Vu)
5694+
#endif /* __HEXAGON_ARCH___ >= 81 */
5695+
5696+
#if __HVX_ARCH__ >= 81
5697+
/* ==========================================================================
5698+
Assembly Syntax: Vdd32.qf16=Vu32.f8
5699+
C Intrinsic Prototype: HVX_VectorPair Q6_Wqf16_equals_V(HVX_Vector Vu)
5700+
Instruction Type: CVI_VP_VS
5701+
Execution Slots: SLOT0123
5702+
========================================================================== */
5703+
5704+
#define Q6_Wqf16_equals_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_f8)(Vu)
5705+
#endif /* __HEXAGON_ARCH___ >= 81 */
5706+
5707+
#if __HVX_ARCH__ >= 81
5708+
/* ==========================================================================
5709+
Assembly Syntax: Vd32.qf16=Vu32.hf
5710+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vhf(HVX_Vector Vu)
5711+
Instruction Type: CVI_VS
5712+
Execution Slots: SLOT0123
5713+
========================================================================== */
5714+
5715+
#define Q6_Vqf16_equals_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_hf)(Vu)
5716+
#endif /* __HEXAGON_ARCH___ >= 81 */
5717+
5718+
#if __HVX_ARCH__ >= 81
5719+
/* ==========================================================================
5720+
Assembly Syntax: Vd32.qf16=Vu32.qf16
5721+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vqf16(HVX_Vector Vu)
5722+
Instruction Type: CVI_VS
5723+
Execution Slots: SLOT0123
5724+
========================================================================== */
5725+
5726+
#define Q6_Vqf16_equals_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_qf16)(Vu)
5727+
#endif /* __HEXAGON_ARCH___ >= 81 */
5728+
5729+
#if __HVX_ARCH__ >= 81
5730+
/* ==========================================================================
5731+
Assembly Syntax: Vd32.qf32=Vu32.qf32
5732+
C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vqf32(HVX_Vector Vu)
5733+
Instruction Type: CVI_VS
5734+
Execution Slots: SLOT0123
5735+
========================================================================== */
5736+
5737+
#define Q6_Vqf32_equals_Vqf32(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_qf32)(Vu)
5738+
#endif /* __HEXAGON_ARCH___ >= 81 */
5739+
5740+
#if __HVX_ARCH__ >= 81
5741+
/* ==========================================================================
5742+
Assembly Syntax: Vd32.qf32=Vu32.sf
5743+
C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vsf(HVX_Vector Vu)
5744+
Instruction Type: CVI_VS
5745+
Execution Slots: SLOT0123
5746+
========================================================================== */
5747+
5748+
#define Q6_Vqf32_equals_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_sf)(Vu)
5749+
#endif /* __HEXAGON_ARCH___ >= 81 */
5750+
5751+
#if __HVX_ARCH__ >= 81
5752+
/* ==========================================================================
5753+
Assembly Syntax: Qd4=vcmp.eq(Vu32.hf,Vv32.hf)
5754+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
5755+
Instruction Type: CVI_VA
5756+
Execution Slots: SLOT0123
5757+
========================================================================== */
5758+
5759+
#define Q6_Q_vcmp_eq_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf)(Vu,Vv)),-1)
5760+
#endif /* __HEXAGON_ARCH___ >= 81 */
5761+
5762+
#if __HVX_ARCH__ >= 81
5763+
/* ==========================================================================
5764+
Assembly Syntax: Qx4&=vcmp.eq(Vu32.hf,Vv32.hf)
5765+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
5766+
Instruction Type: CVI_VA
5767+
Execution Slots: SLOT0123
5768+
========================================================================== */
5769+
5770+
#define Q6_Q_vcmp_eqand_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
5771+
#endif /* __HEXAGON_ARCH___ >= 81 */
5772+
5773+
#if __HVX_ARCH__ >= 81
5774+
/* ==========================================================================
5775+
Assembly Syntax: Qx4|=vcmp.eq(Vu32.hf,Vv32.hf)
5776+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
5777+
Instruction Type: CVI_VA
5778+
Execution Slots: SLOT0123
5779+
========================================================================== */
5780+
5781+
#define Q6_Q_vcmp_eqor_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
5782+
#endif /* __HEXAGON_ARCH___ >= 81 */
5783+
5784+
#if __HVX_ARCH__ >= 81
5785+
/* ==========================================================================
5786+
Assembly Syntax: Qx4^=vcmp.eq(Vu32.hf,Vv32.hf)
5787+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
5788+
Instruction Type: CVI_VA
5789+
Execution Slots: SLOT0123
5790+
========================================================================== */
5791+
5792+
#define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
5793+
#endif /* __HEXAGON_ARCH___ >= 81 */
5794+
5795+
#if __HVX_ARCH__ >= 81
5796+
/* ==========================================================================
5797+
Assembly Syntax: Qd4=vcmp.eq(Vu32.sf,Vv32.sf)
5798+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
5799+
Instruction Type: CVI_VA
5800+
Execution Slots: SLOT0123
5801+
========================================================================== */
5802+
5803+
#define Q6_Q_vcmp_eq_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf)(Vu,Vv)),-1)
5804+
#endif /* __HEXAGON_ARCH___ >= 81 */
5805+
5806+
#if __HVX_ARCH__ >= 81
5807+
/* ==========================================================================
5808+
Assembly Syntax: Qx4&=vcmp.eq(Vu32.sf,Vv32.sf)
5809+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
5810+
Instruction Type: CVI_VA
5811+
Execution Slots: SLOT0123
5812+
========================================================================== */
5813+
5814+
#define Q6_Q_vcmp_eqand_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
5815+
#endif /* __HEXAGON_ARCH___ >= 81 */
5816+
5817+
#if __HVX_ARCH__ >= 81
5818+
/* ==========================================================================
5819+
Assembly Syntax: Qx4|=vcmp.eq(Vu32.sf,Vv32.sf)
5820+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
5821+
Instruction Type: CVI_VA
5822+
Execution Slots: SLOT0123
5823+
========================================================================== */
5824+
5825+
#define Q6_Q_vcmp_eqor_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
5826+
#endif /* __HEXAGON_ARCH___ >= 81 */
5827+
5828+
#if __HVX_ARCH__ >= 81
5829+
/* ==========================================================================
5830+
Assembly Syntax: Qx4^=vcmp.eq(Vu32.sf,Vv32.sf)
5831+
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
5832+
Instruction Type: CVI_VA
5833+
Execution Slots: SLOT0123
5834+
========================================================================== */
5835+
5836+
#define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
5837+
#endif /* __HEXAGON_ARCH___ >= 81 */
5838+
5839+
#if __HVX_ARCH__ >= 81
5840+
/* ==========================================================================
5841+
Assembly Syntax: Vd32.w=vilog2(Vu32.hf)
5842+
C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vhf(HVX_Vector Vu)
5843+
Instruction Type: CVI_VS
5844+
Execution Slots: SLOT0123
5845+
========================================================================== */
5846+
5847+
#define Q6_Vw_vilog2_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_hf)(Vu)
5848+
#endif /* __HEXAGON_ARCH___ >= 81 */
5849+
5850+
#if __HVX_ARCH__ >= 81
5851+
/* ==========================================================================
5852+
Assembly Syntax: Vd32.w=vilog2(Vu32.qf16)
5853+
C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf16(HVX_Vector Vu)
5854+
Instruction Type: CVI_VS
5855+
Execution Slots: SLOT0123
5856+
========================================================================== */
5857+
5858+
#define Q6_Vw_vilog2_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf16)(Vu)
5859+
#endif /* __HEXAGON_ARCH___ >= 81 */
5860+
5861+
#if __HVX_ARCH__ >= 81
5862+
/* ==========================================================================
5863+
Assembly Syntax: Vd32.w=vilog2(Vu32.qf32)
5864+
C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf32(HVX_Vector Vu)
5865+
Instruction Type: CVI_VS
5866+
Execution Slots: SLOT0123
5867+
========================================================================== */
5868+
5869+
#define Q6_Vw_vilog2_Vqf32(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf32)(Vu)
5870+
#endif /* __HEXAGON_ARCH___ >= 81 */
5871+
5872+
#if __HVX_ARCH__ >= 81
5873+
/* ==========================================================================
5874+
Assembly Syntax: Vd32.w=vilog2(Vu32.sf)
5875+
C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vsf(HVX_Vector Vu)
5876+
Instruction Type: CVI_VS
5877+
Execution Slots: SLOT0123
5878+
========================================================================== */
5879+
5880+
#define Q6_Vw_vilog2_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_sf)(Vu)
5881+
#endif /* __HEXAGON_ARCH___ >= 81 */
5882+
5883+
#if __HVX_ARCH__ >= 81
5884+
/* ==========================================================================
5885+
Assembly Syntax: Vd32.qf16=vneg(Vu32.hf)
5886+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vhf(HVX_Vector Vu)
5887+
Instruction Type: CVI_VS
5888+
Execution Slots: SLOT0123
5889+
========================================================================== */
5890+
5891+
#define Q6_Vqf16_vneg_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_hf)(Vu)
5892+
#endif /* __HEXAGON_ARCH___ >= 81 */
5893+
5894+
#if __HVX_ARCH__ >= 81
5895+
/* ==========================================================================
5896+
Assembly Syntax: Vd32.qf16=vneg(Vu32.qf16)
5897+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vqf16(HVX_Vector Vu)
5898+
Instruction Type: CVI_VS
5899+
Execution Slots: SLOT0123
5900+
========================================================================== */
5901+
5902+
#define Q6_Vqf16_vneg_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_qf16)(Vu)
5903+
#endif /* __HEXAGON_ARCH___ >= 81 */
5904+
5905+
#if __HVX_ARCH__ >= 81
5906+
/* ==========================================================================
5907+
Assembly Syntax: Vd32.qf32=vneg(Vu32.qf32)
5908+
C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vqf32(HVX_Vector Vu)
5909+
Instruction Type: CVI_VS
5910+
Execution Slots: SLOT0123
5911+
========================================================================== */
5912+
5913+
#define Q6_Vqf32_vneg_Vqf32(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_qf32)(Vu)
5914+
#endif /* __HEXAGON_ARCH___ >= 81 */
5915+
5916+
#if __HVX_ARCH__ >= 81
5917+
/* ==========================================================================
5918+
Assembly Syntax: Vd32.qf32=vneg(Vu32.sf)
5919+
C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vsf(HVX_Vector Vu)
5920+
Instruction Type: CVI_VS
5921+
Execution Slots: SLOT0123
5922+
========================================================================== */
5923+
5924+
#define Q6_Vqf32_vneg_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_sf)(Vu)
5925+
#endif /* __HEXAGON_ARCH___ >= 81 */
5926+
5927+
#if __HVX_ARCH__ >= 81
5928+
/* ==========================================================================
5929+
Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.qf16)
5930+
C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu, HVX_Vector Vv)
5931+
Instruction Type: CVI_VS
5932+
Execution Slots: SLOT0123
5933+
========================================================================== */
5934+
5935+
#define Q6_Vqf16_vsub_VhfVqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_mix)(Vu,Vv)
5936+
#endif /* __HEXAGON_ARCH___ >= 81 */
5937+
5938+
#if __HVX_ARCH__ >= 81
5939+
/* ==========================================================================
5940+
Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.qf32)
5941+
C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu, HVX_Vector Vv)
5942+
Instruction Type: CVI_VS
5943+
Execution Slots: SLOT0123
5944+
========================================================================== */
5945+
5946+
#define Q6_Vqf32_vsub_VsfVqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_mix)(Vu,Vv)
5947+
#endif /* __HEXAGON_ARCH___ >= 81 */
5948+
56085949
#endif /* __HVX__ */
56095950

56105951
#endif

0 commit comments

Comments
 (0)