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[SelectOpt] Support ADD and SUB with zext operands. (#115489)
Extend the support for implicit selects in the form of OR with a ZExt operand to support ADD and SUB binops as well. They similarly can form implicit selects which can be profitable to convert back the branches. PR: #115489
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-50
lines changed

3 files changed

+109
-50
lines changed

‎llvm/lib/CodeGen/SelectOptimize.cpp‎

Lines changed: 21 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -489,8 +489,10 @@ static Value *getTrueOrFalseValue(
489489
}
490490

491491
auto *BO = cast<BinaryOperator>(SI.getI());
492-
assert(BO->getOpcode() == Instruction::Or &&
493-
"Only currently handling Or instructions.");
492+
assert((BO->getOpcode() == Instruction::Add ||
493+
BO->getOpcode() == Instruction::Or ||
494+
BO->getOpcode() == Instruction::Sub) &&
495+
"Only currently handling Add, Or and Sub binary operators.");
494496

495497
auto *CBO = BO->clone();
496498
auto CondIdx = SI.getConditionOpIndex();
@@ -786,8 +788,23 @@ void SelectOptimizeImpl::collectSelectGroups(BasicBlock &BB,
786788
// An Or(zext(i1 X), Y) can also be treated like a select, with condition X
787789
// and values Y|1 and Y.
788790
if (auto *BO = dyn_cast<BinaryOperator>(I)) {
789-
if (BO->getType()->isIntegerTy(1) || BO->getOpcode() != Instruction::Or)
790-
return SelectInfo.end();
791+
switch (I->getOpcode()) {
792+
case Instruction::Add:
793+
case Instruction::Sub: {
794+
Value *X;
795+
if (!((PatternMatch::match(I->getOperand(0),
796+
m_OneUse(m_ZExt(m_Value(X)))) ||
797+
PatternMatch::match(I->getOperand(1),
798+
m_OneUse(m_ZExt(m_Value(X))))) &&
799+
X->getType()->isIntegerTy(1)))
800+
return SelectInfo.end();
801+
break;
802+
}
803+
case Instruction::Or:
804+
if (BO->getType()->isIntegerTy(1) || BO->getOpcode() != Instruction::Or)
805+
return SelectInfo.end();
806+
break;
807+
}
791808

792809
for (unsigned Idx = 0; Idx < 2; Idx++) {
793810
auto *Op = BO->getOperand(Idx);

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp‎

Lines changed: 14 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4797,14 +4797,20 @@ AArch64TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
47974797
}
47984798

47994799
bool AArch64TTIImpl::shouldTreatInstructionLikeSelect(const Instruction *I) {
4800-
// For the binary operators (e.g. or) we need to be more careful than
4801-
// selects, here we only transform them if they are already at a natural
4802-
// break point in the code - the end of a block with an unconditional
4803-
// terminator.
4804-
if (EnableOrLikeSelectOpt && I->getOpcode() == Instruction::Or &&
4805-
isa<BranchInst>(I->getNextNode()) &&
4806-
cast<BranchInst>(I->getNextNode())->isUnconditional())
4807-
return true;
4800+
if (EnableOrLikeSelectOpt) {
4801+
// For the binary operators (e.g. or) we need to be more careful than
4802+
// selects, here we only transform them if they are already at a natural
4803+
// break point in the code - the end of a block with an unconditional
4804+
// terminator.
4805+
if (I->getOpcode() == Instruction::Or &&
4806+
isa<BranchInst>(I->getNextNode()) &&
4807+
cast<BranchInst>(I->getNextNode())->isUnconditional())
4808+
return true;
4809+
4810+
if (I->getOpcode() == Instruction::Add ||
4811+
I->getOpcode() == Instruction::Sub)
4812+
return true;
4813+
}
48084814
return BaseT::shouldTreatInstructionLikeSelect(I);
48094815
}
48104816

‎llvm/test/CodeGen/AArch64/selectopt-cast.ll‎

Lines changed: 74 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -7,16 +7,22 @@ define void @test_add_zext(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.star
77
; CHECK-NEXT: entry:
88
; CHECK-NEXT: br label [[LOOP:%.*]]
99
; CHECK: loop:
10-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
11-
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
12-
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
10+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[SELECT_END:%.*]] ]
11+
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[SELECT_END]] ]
12+
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[SELECT_END]] ]
1313
; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
1414
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
1515
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
1616
; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
1717
; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
1818
; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[CMP3]] to i64
19-
; CHECK-NEXT: [[J_NEXT]] = add nsw i64 [[J]], [[DEC]]
19+
; CHECK-NEXT: [[CMP3_FROZEN:%.*]] = freeze i1 [[CMP3]]
20+
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_TRUE_SINK:%.*]], label [[SELECT_END]]
21+
; CHECK: select.true.sink:
22+
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[J]], 1
23+
; CHECK-NEXT: br label [[SELECT_END]]
24+
; CHECK: select.end:
25+
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[TMP0]], [[SELECT_TRUE_SINK]] ], [ [[J]], [[LOOP]] ]
2026
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
2127
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
2228
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
@@ -54,20 +60,26 @@ define void @test_add_zext_first_op(ptr %dst, ptr %src, i64 %j.start, i64 %p, i6
5460
; CHECK-NEXT: entry:
5561
; CHECK-NEXT: br label [[LOOP:%.*]]
5662
; CHECK: loop:
57-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
58-
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
59-
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
60-
; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
61-
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
62-
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
63+
; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[SELECT_END:%.*]] ]
64+
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[SELECT_END]] ]
65+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[SELECT_END]] ]
66+
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
67+
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_DST]], align 8
68+
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[DST]], i64 [[J]]
6369
; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
6470
; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
6571
; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[CMP3]] to i64
66-
; CHECK-NEXT: [[J_NEXT]] = add nsw i64 [[DEC]], [[J]]
67-
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
68-
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
69-
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
70-
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[J_START]]
72+
; CHECK-NEXT: [[CMP3_FROZEN:%.*]] = freeze i1 [[CMP3]]
73+
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_TRUE_SINK:%.*]], label [[SELECT_END]]
74+
; CHECK: select.true.sink:
75+
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 1, [[J]]
76+
; CHECK-NEXT: br label [[SELECT_END]]
77+
; CHECK: select.end:
78+
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[TMP0]], [[SELECT_TRUE_SINK]] ], [ [[J]], [[LOOP]] ]
79+
; CHECK-NEXT: [[GEP_DST1:%.*]] = getelementptr inbounds ptr, ptr [[DST1:%.*]], i64 [[IV1]]
80+
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST1]], align 8
81+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV1]], 1
82+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV1]], [[J_START]]
7183
; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP]]
7284
; CHECK: exit:
7385
; CHECK-NEXT: ret void
@@ -101,17 +113,23 @@ define void @test_add_zext_not(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.
101113
; CHECK-NEXT: entry:
102114
; CHECK-NEXT: br label [[LOOP:%.*]]
103115
; CHECK: loop:
104-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
105-
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
106-
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
116+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[SELECT_END:%.*]] ]
117+
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[SELECT_END]] ]
118+
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[SELECT_END]] ]
107119
; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
108120
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
109121
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
110122
; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
111123
; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
112124
; CHECK-NEXT: [[NOT_CMP3:%.*]] = xor i1 [[CMP3]], true
113125
; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[NOT_CMP3]] to i64
114-
; CHECK-NEXT: [[J_NEXT]] = add nsw i64 [[J]], [[DEC]]
126+
; CHECK-NEXT: [[CMP3_FROZEN:%.*]] = freeze i1 [[CMP3]]
127+
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_END]], label [[SELECT_FALSE_SINK:%.*]]
128+
; CHECK: select.false.sink:
129+
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[J]], 1
130+
; CHECK-NEXT: br label [[SELECT_END]]
131+
; CHECK: select.end:
132+
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[J]], [[LOOP]] ], [ [[TMP0]], [[SELECT_FALSE_SINK]] ]
115133
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
116134
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
117135
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
@@ -356,16 +374,22 @@ define void @test_sub_zext(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.star
356374
; CHECK-NEXT: entry:
357375
; CHECK-NEXT: br label [[LOOP:%.*]]
358376
; CHECK: loop:
359-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
360-
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
361-
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
377+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[SELECT_END:%.*]] ]
378+
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[HIGH:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[SELECT_END]] ]
379+
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[SELECT_END]] ]
362380
; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
363381
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
364382
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
365383
; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
366384
; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
367385
; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[CMP3]] to i64
368-
; CHECK-NEXT: [[J_NEXT]] = sub nsw i64 [[J]], [[DEC]]
386+
; CHECK-NEXT: [[CMP3_FROZEN:%.*]] = freeze i1 [[CMP3]]
387+
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_TRUE_SINK:%.*]], label [[SELECT_END]]
388+
; CHECK: select.true.sink:
389+
; CHECK-NEXT: [[TMP0:%.*]] = sub nsw i64 [[J]], 1
390+
; CHECK-NEXT: br label [[SELECT_END]]
391+
; CHECK: select.end:
392+
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[TMP0]], [[SELECT_TRUE_SINK]] ], [ [[J]], [[LOOP]] ]
369393
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
370394
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
371395
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
@@ -403,20 +427,26 @@ define void @test_sub_zext_first_op(ptr %dst, ptr %src, i64 %j.start, i64 %p, i6
403427
; CHECK-NEXT: entry:
404428
; CHECK-NEXT: br label [[LOOP:%.*]]
405429
; CHECK: loop:
406-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
407-
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
408-
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
409-
; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
410-
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
411-
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
430+
; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[SELECT_END:%.*]] ]
431+
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[SELECT_END]] ]
432+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[SELECT_END]] ]
433+
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
434+
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_DST]], align 8
435+
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[DST]], i64 [[J]]
412436
; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
413437
; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
414438
; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[CMP3]] to i64
415-
; CHECK-NEXT: [[J_NEXT]] = sub nsw i64 [[DEC]], [[J]]
416-
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
417-
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
418-
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
419-
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[J_START]]
439+
; CHECK-NEXT: [[CMP3_FROZEN:%.*]] = freeze i1 [[CMP3]]
440+
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_TRUE_SINK:%.*]], label [[SELECT_END]]
441+
; CHECK: select.true.sink:
442+
; CHECK-NEXT: [[TMP0:%.*]] = sub nsw i64 1, [[J]]
443+
; CHECK-NEXT: br label [[SELECT_END]]
444+
; CHECK: select.end:
445+
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[TMP0]], [[SELECT_TRUE_SINK]] ], [ [[J]], [[LOOP]] ]
446+
; CHECK-NEXT: [[GEP_DST1:%.*]] = getelementptr inbounds ptr, ptr [[DST1:%.*]], i64 [[IV1]]
447+
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST1]], align 8
448+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV1]], 1
449+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV1]], [[J_START]]
420450
; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP]]
421451
; CHECK: exit:
422452
; CHECK-NEXT: ret void
@@ -450,17 +480,23 @@ define void @test_sub_zext_not(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.
450480
; CHECK-NEXT: entry:
451481
; CHECK-NEXT: br label [[LOOP:%.*]]
452482
; CHECK: loop:
453-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
454-
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
455-
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
483+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[SELECT_END:%.*]] ]
484+
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[SELECT_END]] ]
485+
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[SELECT_END]] ]
456486
; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
457487
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
458488
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
459489
; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
460490
; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
461491
; CHECK-NEXT: [[NOT_CMP3:%.*]] = xor i1 [[CMP3]], true
462492
; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[NOT_CMP3]] to i64
463-
; CHECK-NEXT: [[J_NEXT]] = sub nsw i64 [[J]], [[DEC]]
493+
; CHECK-NEXT: [[CMP3_FROZEN:%.*]] = freeze i1 [[CMP3]]
494+
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_END]], label [[SELECT_FALSE_SINK:%.*]]
495+
; CHECK: select.false.sink:
496+
; CHECK-NEXT: [[TMP0:%.*]] = sub nsw i64 [[J]], 1
497+
; CHECK-NEXT: br label [[SELECT_END]]
498+
; CHECK: select.end:
499+
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[J]], [[LOOP]] ], [ [[TMP0]], [[SELECT_FALSE_SINK]] ]
464500
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
465501
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
466502
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1

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