Adjust latency and remove --all-stats

Author: wangpc-pp

llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td

@@ -10,19 +10,19 @@
 // We assume that:
 // * 6-issue out-of-order CPU with 192 ROB entries.
 // * Units:
-//   * IXU (Integer GenericOOOALU Unit): 4 units, only one can execute division.
+//   * IXU (Integer ALU Unit): 4 units, only one can execute division.
 //   * FXU (Floating-point Unit): 2 units.
 //   * LSU (Load/Store Unit): 2 units.
 //   * VXU (Vector Unit): 1 unit.
 // * Latency:
 //   * Integer instructions: 1 cycle.
 //   * Multiplication instructions: 4 cycles.
 //   * Multiplication/Division instructions: 7-13 cycles.
-//   * Floating-point instructions: 4-6 cycles.
+//   * Floating-point instructions: 2-6 cycles.
 //   * Vector instructions: 2-6 cycles.
 //   * Load/Store:
 //     * IXU: 4 cycles.
-//     * FXU: 6 cycles.
+//     * FXU: 4 cycles.
 //     * VXU: 6 cycles.
 // * Integer/floating-point/vector div/rem/sqrt/... are non-pipelined.
 //===----------------------------------------------------------------------===//
@@ -129,7 +129,7 @@ def : WriteRes<WriteAtomicSTD, [GenericOOOLSU]>;
 // Floating-point
 //===----------------------------------------------------------------------===//
 // Floating-point load
-let Latency = 6 in {
+let Latency = 4 in {
   def : WriteRes<WriteFLD32, [GenericOOOLSU]>;
   def : WriteRes<WriteFLD64, [GenericOOOLSU]>;
 }
@@ -139,12 +139,12 @@ def : WriteRes<WriteFST32, [GenericOOOLSU]>;
 def : WriteRes<WriteFST64, [GenericOOOLSU]>;
 
 // Arithmetic and logic
-let Latency = 4 in {
+let Latency = 2 in {
   def : WriteRes<WriteFAdd32, [GenericOOOFPU]>;
   def : WriteRes<WriteFAdd64, [GenericOOOFPU]>;
 }
 
-let Latency = 5 in {
+let Latency = 4 in {
   def : WriteRes<WriteFMul32, [GenericOOOFPU]>;
   def : WriteRes<WriteFMul64, [GenericOOOFPU]>;
 }
@@ -177,29 +177,29 @@ let Latency = 17, ReleaseAtCycles = [17] in {
 }
 
 // Conversions
-let Latency = 4 in {
+let Latency = 2 in {
   def : WriteRes<WriteFCvtI32ToF32, [GenericOOOFPU]>;
   def : WriteRes<WriteFCvtI32ToF64, [GenericOOOFPU]>;
   def : WriteRes<WriteFCvtI64ToF32, [GenericOOOFPU]>;
   def : WriteRes<WriteFCvtI64ToF64, [GenericOOOFPU]>;
 }
 
-let Latency = 4 in {
+let Latency = 2 in {
   def : WriteRes<WriteFCvtF32ToI32, [GenericOOOFPU]>;
   def : WriteRes<WriteFCvtF32ToI64, [GenericOOOFPU]>;
 }
 
-let Latency = 4 in {
+let Latency = 2 in {
   def : WriteRes<WriteFCvtF64ToI32, [GenericOOOFPU]>;
   def : WriteRes<WriteFCvtF64ToI64, [GenericOOOFPU]>;
 }
 
-let Latency = 4 in {
+let Latency = 2 in {
   def : WriteRes<WriteFCvtF64ToF32, [GenericOOOFPU]>;
   def : WriteRes<WriteFCvtF32ToF64, [GenericOOOFPU]>;
 }
 
-let Latency = 6 in {
+let Latency = 2 in {
   def : WriteRes<WriteFMovI32ToF32, [GenericOOOFPU]>;
   def : WriteRes<WriteFMovI64ToF64, [GenericOOOFPU]>;
   def : WriteRes<WriteFMovF32ToI32, [GenericOOOFPU]>;
@@ -275,13 +275,13 @@ def : WriteRes<WriteXPERM, [GenericOOOALU]>;
 //===----------------------------------------------------------------------===//
 // Zfa extension
 //===----------------------------------------------------------------------===//
-let Latency = 3 in {
+let Latency = 2 in {
   def : WriteRes<WriteFRoundF16, [GenericOOOFPU]>;
   def : WriteRes<WriteFRoundF32, [GenericOOOFPU]>;
   def : WriteRes<WriteFRoundF64, [GenericOOOFPU]>;
 }
 
-let Latency = 5 in {
+let Latency = 2 in {
   def : WriteRes<WriteFLI16, [GenericOOOFPU]>;
   def : WriteRes<WriteFLI32, [GenericOOOFPU]>;
   def : WriteRes<WriteFLI64, [GenericOOOFPU]>;
@@ -292,36 +292,36 @@ let Latency = 5 in {
 //===----------------------------------------------------------------------===//
 // Zfhmin
 // Load/Store
-let Latency = 6 in
+let Latency = 4 in
 def : WriteRes<WriteFLD16, [GenericOOOLSU]>;
 def : WriteRes<WriteFST16, [GenericOOOLSU]>;
 
 // Conversions
-let Latency = 3 in {
+let Latency = 2 in {
   def : WriteRes<WriteFCvtF16ToF64, [GenericOOOFPU]>;
   def : WriteRes<WriteFCvtF64ToF16, [GenericOOOFPU]>;
   def : WriteRes<WriteFCvtF32ToF16, [GenericOOOFPU]>;
   def : WriteRes<WriteFCvtF16ToF32, [GenericOOOFPU]>;
 }
 
-let Latency = 4 in {
+let Latency = 2 in {
   def : WriteRes<WriteFMovI16ToF16, [GenericOOOFPU]>;
   def : WriteRes<WriteFMovF16ToI16, [GenericOOOFPU]>;
 }
 
 // Other than Zfhmin
-let Latency = 4 in {
+let Latency = 2 in {
   def : WriteRes<WriteFCvtI64ToF16, []>;
   def : WriteRes<WriteFCvtI32ToF16, []>;
   def : WriteRes<WriteFCvtF16ToI64, []>;
   def : WriteRes<WriteFCvtF16ToI32, []>;
 }
 
 // Arithmetic and logic
-let Latency = 4 in
+let Latency = 2 in
 def : WriteRes<WriteFAdd16, [GenericOOOFPU]>;
 
-let Latency = 5 in
+let Latency = 4 in
 def : WriteRes<WriteFMul16, [GenericOOOFPU]>;
 
 let Latency = 6 in

llvm/test/tools/llvm-mca/RISCV/GenericOOO/atomic.s

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mattr=+rva23u64,+zabha -mcpu=generic-ooo --all-stats -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mattr=+rva23u64,+zabha -mcpu=generic-ooo -iterations=1 < %s | FileCheck %s
 
 # Zalrsc
 lr.w t0, (t1)
@@ -384,45 +384,6 @@ amomaxu.h.aqrl s5, s4, (s3)
 # CHECK-NEXT:  1      5     0.50    *      *            amominu.h.aqrl	s6, s5, (s4)
 # CHECK-NEXT:  1      5     0.50    *      *            amomaxu.h.aqrl	s5, s4, (s3)
 
-# CHECK:      Dynamic Dispatch Stall Cycles:
-# CHECK-NEXT: RAT     - Register unavailable:                      0
-# CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
-# CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
-# CHECK-NEXT: LQ      - Load queue full:                           0
-# CHECK-NEXT: SQ      - Store queue full:                          0
-# CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
-# CHECK-NEXT: USH     - Uncategorised Structural Hazard:           0
-
-# CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
-# CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              121  (81.8%)
-# CHECK-NEXT:  4,              1  (0.7%)
-# CHECK-NEXT:  6,              26  (17.6%)
-
-# CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
-# CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          58  (39.2%)
-# CHECK-NEXT:  1,          20  (13.5%)
-# CHECK-NEXT:  2,          70  (47.3%)
-
-# CHECK:      Scheduler's queue usage:
-# CHECK-NEXT: No scheduler resources used.
-
-# CHECK:      Retire Control Unit - number of cycles where we saw N instructions retired:
-# CHECK-NEXT: [# retired], [# cycles]
-# CHECK-NEXT:  0,           58  (39.2%)
-# CHECK-NEXT:  1,           22  (14.9%)
-# CHECK-NEXT:  2,           66  (44.6%)
-# CHECK-NEXT:  3,           2  (1.4%)
-
-# CHECK:      Total ROB Entries:                192
-# CHECK-NEXT: Max Used ROB Entries:             136  ( 70.8% )
-# CHECK-NEXT: Average Used ROB Entries per cy:  69  ( 35.9% )
-
-# CHECK:      Register File statistics:
-# CHECK-NEXT: Total number of mappings created:    160
-# CHECK-NEXT: Max number of mappings used:         136
-
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - GenericOOODIV
 # CHECK-NEXT: [1.0] - GenericOOOFPU