@@ -713,12 +713,13 @@ foreach m = [1, 2, 4] in {
713713 }
714714}
715715
716- class VReg<list<ValueType> regTypes, dag regList, int Vlmul>
716+ class VReg<list<ValueType> regTypes, dag regList, int Vlmul, int nf = 1 >
717717 : RISCVRegisterClass<regTypes,
718718 64, // The maximum supported ELEN is 64.
719719 regList> {
720720 let IsVRegClass = 1;
721721 let VLMul = Vlmul;
722+ let NF = nf;
722723}
723724
724725defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t,
@@ -799,17 +800,15 @@ class VTupRegList<int LMUL, int NF> {
799800
800801foreach m = LMULList in {
801802 foreach nf = NFList<m>.L in {
802- let NF = nf in {
803- def "VRN" # nf # "M" # m # "NoV0"
804- : VReg<VTupRegList<m, nf>.L,
805- (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
806- m>;
807- def "VRN" # nf # "M" # m
808- : VReg<VTupRegList<m, nf>.L,
809- (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0"),
810- !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")),
811- m>;
812- }
803+ def "VRN" # nf # "M" # m # "NoV0"
804+ : VReg<VTupRegList<m, nf>.L,
805+ (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
806+ m, nf>;
807+ def "VRN" # nf # "M" # m
808+ : VReg<VTupRegList<m, nf>.L,
809+ (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0"),
810+ !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")),
811+ m, nf>;
813812 }
814813}
815814
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