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Add test case
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‎llvm/test/CodeGen/AArch64/switch-cases-to-branch-and.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -O3 -mtriple=arm64-apple-macosx -o - %s | FileCheck %s
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define i32 @switch_with_matching_dests_0_and_pow2_3_cases(i8 %v) {
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; CHECK-LABEL: switch_with_matching_dests_0_and_pow2_3_cases:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: mov w9, #100 ; =0x64
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; CHECK-NEXT: mov w8, #20 ; =0x14
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; CHECK-NEXT: LBB0_1: ; %loop.header
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ands w10, w0, #0xff
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; CHECK-NEXT: b.eq LBB0_6
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; CHECK-NEXT: ; %bb.2: ; %loop.header
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; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: cmp w10, #32
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; CHECK-NEXT: b.eq LBB0_6
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; CHECK-NEXT: ; %bb.3: ; %loop.header
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; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: cmp w10, #124
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; CHECK-NEXT: b.eq LBB0_7
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; CHECK-NEXT: ; %bb.4: ; %loop.latch
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; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: subs w9, w9, #1
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; CHECK-NEXT: b.ne LBB0_1
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; CHECK-NEXT: ; %bb.5:
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; CHECK-NEXT: mov w8, #20 ; =0x14
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; CHECK-NEXT: LBB0_6: ; %common.ret
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; CHECK-NEXT: mov w0, w8
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB0_7: ; %e2
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; CHECK-NEXT: mov w0, #30 ; =0x1e
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; CHECK-NEXT: ret
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
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switch i8 %v, label %loop.latch [
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i8 32, label %e1
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i8 0, label %e1
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i8 124, label %e2
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]
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loop.latch:
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%iv.next = add i32 %iv, 1
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%c = icmp eq i32 %iv.next, 100
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br i1 %c, label %e1, label %loop.header
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e1:
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ret i32 20
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e2:
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ret i32 30
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}
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define i64 @consecutive_match_both(ptr %p, i32 %param) {
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; CHECK-LABEL: consecutive_match_both:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: mov w8, #1 ; =0x1
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; CHECK-NEXT: mov w9, #100 ; =0x64
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; CHECK-NEXT: mov w10, #249 ; =0xf9
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: b LBB1_2
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; CHECK-NEXT: LBB1_1: ; %loop.latch
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; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: subs w9, w9, #1
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; CHECK-NEXT: b.eq LBB1_5
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; CHECK-NEXT: LBB1_2: ; %loop.header
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmp w1, #7
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; CHECK-NEXT: b.hi LBB1_1
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; CHECK-NEXT: ; %bb.3: ; %loop.header
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; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: tst w8, w10
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; CHECK-NEXT: b.eq LBB1_1
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; CHECK-NEXT: ; %bb.4: ; %e0
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB1_5:
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; CHECK-NEXT: mov x0, #-42 ; =0xffffffffffffffd6
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; CHECK-NEXT: ret
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
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switch i32 %param, label %loop.latch [
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i32 7, label %e0
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i32 6, label %e0
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i32 5, label %e0
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i32 4, label %e0
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i32 3, label %e0
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i32 0, label %e0
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]
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loop.latch:
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%iv.next = add i32 %iv, 1
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%ec = icmp eq i32 %iv.next, 100
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br i1 %ec, label %e1, label %loop.header
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e0:
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%m = getelementptr i8, ptr %p, i64 20
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br label %e1
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e1:
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%res = phi i64 [ 0, %e0 ], [ -42, %loop.latch ]
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ret i64 %res
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}
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define i64 @consecutive_match_before(ptr %p, i32 %param) {
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; CHECK-LABEL: consecutive_match_before:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: mov w8, #1 ; =0x1
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; CHECK-NEXT: mov w9, #100 ; =0x64
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; CHECK-NEXT: mov w10, #25 ; =0x19
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: b LBB2_2
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; CHECK-NEXT: LBB2_1: ; %loop.latch
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; CHECK-NEXT: ; in Loop: Header=BB2_2 Depth=1
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; CHECK-NEXT: subs w9, w9, #1
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; CHECK-NEXT: b.eq LBB2_5
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; CHECK-NEXT: LBB2_2: ; %loop.header
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmp w1, #4
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; CHECK-NEXT: b.hi LBB2_1
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; CHECK-NEXT: ; %bb.3: ; %loop.header
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; CHECK-NEXT: ; in Loop: Header=BB2_2 Depth=1
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; CHECK-NEXT: tst w8, w10
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; CHECK-NEXT: b.eq LBB2_1
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; CHECK-NEXT: ; %bb.4: ; %e0
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB2_5:
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; CHECK-NEXT: mov x0, #-42 ; =0xffffffffffffffd6
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; CHECK-NEXT: ret
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
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switch i32 %param, label %loop.latch [
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i32 4, label %e0
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i32 3, label %e0
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i32 0, label %e0
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]
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loop.latch:
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%iv.next = add i32 %iv, 1
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%ec = icmp eq i32 %iv.next, 100
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br i1 %ec, label %e1, label %loop.header
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e0:
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%m = getelementptr i8, ptr %p, i64 20
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br label %e1
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e1:
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%res = phi i64 [ 0, %e0 ], [ -42, %loop.latch ]
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ret i64 %res
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}
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define i64 @consecutive_match_after(ptr %p, i32 %param) {
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; CHECK-LABEL: consecutive_match_after:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: mov w8, #1 ; =0x1
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; CHECK-NEXT: mov w9, #100 ; =0x64
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; CHECK-NEXT: mov w10, #49 ; =0x31
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: b LBB3_2
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; CHECK-NEXT: LBB3_1: ; %loop.latch
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; CHECK-NEXT: ; in Loop: Header=BB3_2 Depth=1
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; CHECK-NEXT: subs w9, w9, #1
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; CHECK-NEXT: b.eq LBB3_5
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; CHECK-NEXT: LBB3_2: ; %loop.header
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmp w1, #5
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; CHECK-NEXT: b.hi LBB3_1
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; CHECK-NEXT: ; %bb.3: ; %loop.header
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; CHECK-NEXT: ; in Loop: Header=BB3_2 Depth=1
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; CHECK-NEXT: tst w8, w10
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; CHECK-NEXT: b.eq LBB3_1
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; CHECK-NEXT: ; %bb.4: ; %e0
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB3_5:
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; CHECK-NEXT: mov x0, #-42 ; =0xffffffffffffffd6
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; CHECK-NEXT: ret
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
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switch i32 %param, label %loop.latch [
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i32 5, label %e0
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i32 4, label %e0
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i32 0, label %e0
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]
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loop.latch:
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%iv.next = add i32 %iv, 1
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%ec = icmp eq i32 %iv.next, 100
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br i1 %ec, label %e1, label %loop.header
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e0:
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%m = getelementptr i8, ptr %p, i64 20
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br label %e1
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e1:
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%res = phi i64 [ 0, %e0 ], [ -42, %loop.latch ]
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ret i64 %res
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}

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