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[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension
The Qualcomm uC Xqcicm extension adds 13 conditional move instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. Change-Id: I301fffd3223b48e32658ef85d602dbb9d50a2a57
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -191,6 +191,7 @@
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// CHECK-NEXT: xqcia 0.2 'Xqcia' (Qualcomm uC Arithmetic Extension)
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// CHECK-NEXT: xqciac 0.2 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)
193193
// CHECK-NEXT: xqcicli 0.2 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)
194+
// CHECK-NEXT: xqcicm 0.2 'Xqcicm' (Qualcomm uC Conditional Move Extension)
194195
// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
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// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
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// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)

‎llvm/docs/RISCVUsage.rst‎

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@@ -435,6 +435,9 @@ The current vendor extensions supported are:
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``experimental-Xqcicli``
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LLVM implements `version 0.2 of the Qualcomm uC Conditional Load Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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438+
``experimental-Xqcicm``
439+
LLVM implements `version 0.2 of the Qualcomm uC Conditional Move extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcics``
439442
LLVM implements `version 0.2 of the Qualcomm uC Conditional Select extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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‎llvm/docs/ReleaseNotes.md‎

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@@ -232,6 +232,8 @@ Changes to the RISC-V Backend
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcicli` (Conditional Load Immediate)
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcicm` (Conditonal Move)
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extension.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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@@ -698,6 +698,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
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TRY_TO_DECODE_FEATURE(
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RISCV::FeatureVendorXqcicli, DecoderTableXqcicli32,
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"Qualcomm uC Conditional Load Immediate custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicm, DecoderTableXqcicm32,
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"Qualcomm uC Conditional Move custom opcode table");
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TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
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return MCDisassembler::Fail;
@@ -727,6 +729,9 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
727729
TRY_TO_DECODE_FEATURE(
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RISCV::FeatureVendorXqciac, DecoderTableXqciac16,
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"Qualcomm uC Load-Store Address Calculation custom 16bit opcode table");
732+
TRY_TO_DECODE_FEATURE(
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RISCV::FeatureVendorXqcicm, DecoderTableXqcicm16,
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"Qualcomm uC Conditional Move custom 16bit opcode table");
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TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureVendorXwchc),
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DecoderTableXwchc16,
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"WCH QingKe XW custom opcode table");

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1290,6 +1290,14 @@ def HasVendorXqcicli
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AssemblerPredicate<(all_of FeatureVendorXqcicli),
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"'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)">;
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def FeatureVendorXqcicm
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: RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Move Extension",
1295+
[FeatureStdExtZca]>;
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def HasVendorXqcicm
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: Predicate<"Subtarget->hasVendorXqcicm()">,
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AssemblerPredicate<(all_of FeatureVendorXqcicm),
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"'Xqcicm' (Qualcomm uC Conditional Move Extension)">;
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//===----------------------------------------------------------------------===//
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// LLVM specific features and extensions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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@@ -150,6 +150,33 @@ class QCILICC<bits<3> funct3, bits<2> funct2, DAGOperand InTyRs2, string opcodes
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let Inst{31-25} = {simm, funct2};
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class QCIMVCC<bits<3> funct3, string opcodestr>
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: RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd),
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(ins GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3),
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opcodestr, "$rd, $rs1, $rs2, $rs3"> {
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class QCIMVCCI<bits<3> funct3, string opcodestr>
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: RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd),
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(ins GPRNoX0:$rs1, simm5:$imm, GPRNoX0:$rs3),
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opcodestr, "$rd, $rs1, $imm, $rs3"> {
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bits<5> imm;
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let rs2 = imm;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class QCIMVCCUI<bits<3> funct3, string opcodestr>
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: RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd),
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(ins GPRNoX0:$rs1, uimm5:$imm, GPRNoX0:$rs3),
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opcodestr, "$rd, $rs1, $imm, $rs3"> {
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bits<5> imm;
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let rs2 = imm;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
@@ -270,6 +297,42 @@ let Predicates = [HasVendorXqcicli, IsRV32], DecoderNamespace = "Xqcicli" in {
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def QC_LIGEUI : QCILICC<0b111, 0b11, uimm5, "qc.ligeui">;
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} // Predicates = [HasVendorXqcicli, IsRV32], DecoderNamespace = "Xqcicli"
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let Predicates = [HasVendorXqcicm, IsRV32], DecoderNamespace = "Xqcicm" in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def QC_C_MVEQZ : RVInst16CL<0b101, 0b10, (outs GPRC:$rd_wb),
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(ins GPRC:$rd, GPRC:$rs1),
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"qc.c.mveqz", "$rd, $rs1"> {
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let Constraints = "$rd = $rd_wb";
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let Inst{12-10} = 0b011;
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let Inst{6-5} = 0b00;
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}
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def QC_MVEQ : QCIMVCC<0b000, "qc.mveq">;
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def QC_MVNE : QCIMVCC<0b001, "qc.mvne">;
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def QC_MVLT : QCIMVCC<0b100, "qc.mvlt">;
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def QC_MVGE : QCIMVCC<0b101, "qc.mvge">;
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def QC_MVLTU : QCIMVCC<0b110, "qc.mvltu">;
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def QC_MVGEU : QCIMVCC<0b111, "qc.mvgeu">;
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def QC_MVEQI : QCIMVCCI <0b000, "qc.mveqi">;
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def QC_MVNEI : QCIMVCCI <0b001, "qc.mvnei">;
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def QC_MVLTI : QCIMVCCI <0b100, "qc.mvlti">;
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def QC_MVGEI : QCIMVCCI <0b101, "qc.mvgei">;
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def QC_MVLTUI : QCIMVCCUI<0b110, "qc.mvltui">;
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def QC_MVGEUI : QCIMVCCUI<0b111, "qc.mvgeui">;
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} // Predicates = [HasVendorXqcicm, IsRV32], DecoderNamespace = "Xqcicm"
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//===----------------------------------------------------------------------===//
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// Aliases
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//===----------------------------------------------------------------------===//

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

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@@ -742,8 +742,8 @@ Error RISCVISAInfo::checkDependency() {
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bool HasZvl = MinVLen != 0;
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bool HasZcmt = Exts.count("zcmt") != 0;
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static constexpr StringLiteral XqciExts[] = {
745-
{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcics"},
746-
{"xqcicsr"}, {"xqcilsm"}, {"xqcisls"}};
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{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"},
746+
{"xqcics"}, {"xqcicsr"}, {"xqcilsm"}, {"xqcisls"}};
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if (HasI && HasE)
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return getIncompatibleError("i", "e");

‎llvm/test/CodeGen/RISCV/attributes.ll‎

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@@ -84,6 +84,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcia %s -o - | FileCheck --check-prefix=RV32XQCIA %s
8585
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciac %s -o - | FileCheck --check-prefix=RV32XQCIAC %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli %s -o - | FileCheck --check-prefix=RV32XQCICLI %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm %s -o - | FileCheck --check-prefix=RV32XQCICM %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s
@@ -395,6 +396,7 @@
395396
; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p2"
396397
; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p2"
397398
; RV32XQCICLI: .attribute 5, "rv32i2p1_xqcicli0p2"
399+
; RV32XQCICM: .attribute 5, "rv32i2p1_zca1p0_xqcicm0p2"
398400
; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
399401
; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
400402
; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"

‎llvm/test/MC/RISCV/xqcicm-invalid.s‎

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# Xqcicm - Qualcomm uC Conditional Move Extension
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcicm < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-IMM %s
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# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicm < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-EXT %s
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# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
8+
qc.c.mveqz 9, x10
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.c.mveqz x9
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13+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension)
14+
qc.c.mveqz x9, x10
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16+
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# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction
18+
qc.mveq 9, x10, x11, x12
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.mveq x9
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# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension)
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qc.mveq x9, x10, x11, x12
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# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction
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qc.mvge 9, x10, x11, x12
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.mvge x9
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33+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension)
34+
qc.mvge x9, x10, x11, x12
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36+
37+
# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
38+
qc.mvgeu 9, x10, x11, x12
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40+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
41+
qc.mvgeu x9
42+
43+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension)
44+
qc.mvgeu x9, x10, x11, x12
45+
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47+
# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction
48+
qc.mvlt 9, x10, x11, x12
49+
50+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
51+
qc.mvlt x9
52+
53+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension)
54+
qc.mvlt x9, x10, x11, x12
55+
56+
57+
# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
58+
qc.mvltu 9, x10, x11, x12
59+
60+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
61+
qc.mvltu x9
62+
63+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension)
64+
qc.mvltu x9, x10, x11, x12
65+
66+
67+
# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction
68+
qc.mvne 9, x10, x11, x12
69+
70+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
71+
qc.mvne x9
72+
73+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension)
74+
qc.mvne x9, x10, x11, x12
75+
76+
77+
# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
78+
qc.mveqi 9, x10, 5, x12
79+
80+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
81+
qc.mveqi x9
82+
83+
# CHECK-IMM: :[[@LINE+1]]:19: error: immediate must be an integer in the range [-16, 15]
84+
qc.mveqi x9, x10, 17, x12
85+
86+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension)
87+
qc.mveqi x9, x10, 5, x12
88+
89+
90+
# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
91+
qc.mvgei 9, x10, 5, x12
92+
93+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
94+
qc.mvgei x9
95+
96+
# CHECK-IMM: :[[@LINE+1]]:19: error: immediate must be an integer in the range [-16, 15]
97+
qc.mvgei x9, x10, 17, x12
98+
99+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension)
100+
qc.mvgei x9, x10, 5, x12
101+
102+
103+
# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
104+
qc.mvlti 9, x10, 5, x12
105+
106+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
107+
qc.mvlti x9
108+
109+
# CHECK-IMM: :[[@LINE+1]]:19: error: immediate must be an integer in the range [-16, 15]
110+
qc.mvlti x9, x10, 17, x12
111+
112+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension)
113+
qc.mvlti x9, x10, 5, x12
114+
115+
116+
# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
117+
qc.mvnei 9, x10, 5, x12
118+
119+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
120+
qc.mvnei x9
121+
122+
# CHECK-IMM: :[[@LINE+1]]:19: error: immediate must be an integer in the range [-16, 15]
123+
qc.mvnei x9, x10, 17, x12
124+
125+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension)
126+
qc.mvnei x9, x10, 5, x12
127+
128+
129+
# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
130+
qc.mvltui 9, x10, 5, x12
131+
132+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
133+
qc.mvltui x9
134+
135+
# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 31]
136+
qc.mvltui x9, x10, 37, x12
137+
138+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension)
139+
qc.mvltui x9, x10, 5, x12
140+
141+
142+
# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
143+
qc.mvgeui 9, x10, 5, x12
144+
145+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
146+
qc.mvgeui x9
147+
148+
# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 31]
149+
qc.mvgeui x9, x10, 37, x12
150+
151+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicm' (Qualcomm uC Conditional Move Extension)
152+
qc.mvgeui x9, x10, 5, x12

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