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SamTebbs33SamTebbs33
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Fix RISCV tests
1 parent fcd46af commit 9a54b56

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3 files changed

+29
-16
lines changed

3 files changed

+29
-16
lines changed

‎llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,8 @@
33

44
define void @add(ptr noalias nocapture readonly %src1, ptr noalias nocapture readonly %src2, i32 signext %size, ptr noalias nocapture writeonly %result) {
55
; CHECK-LABEL: add
6-
; CHECK: LV(REG): Found max usage: 2 item
6+
; CHECK: LV(REG): VF = 8
7+
; CHECK-NEXT: LV(REG): Found max usage: 2 item
78
; CHECK-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
89
; CHECK-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
910
; CHECK-NEXT: LV(REG): Found invariant usage: 1 item

‎llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,14 @@
44

55
define void @add(ptr noalias nocapture readonly %src1, ptr noalias nocapture readonly %src2, i32 signext %size, ptr noalias nocapture writeonly %result) {
66
; CHECK-LABEL: add
7-
; ZVFH: LV(REG): Found max usage: 2 item
7+
; ZVFH: LV(REG): VF = 8
8+
; ZVFH-NEXT: LV(REG): Found max usage: 2 item
89
; ZVFH-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
910
; ZVFH-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
1011
; ZVFH-NEXT: LV(REG): Found invariant usage: 1 item
1112
; ZVFH-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
12-
; ZVFHMIN: LV(REG): Found max usage: 2 item
13+
; ZVFHMIN: LV(REG): VF = 8
14+
; ZVFHMIN-NEXT: LV(REG): Found max usage: 2 item
1315
; ZVFHMIN-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
1416
; ZVFHMIN-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
1517
; ZVFHMIN-NEXT: LV(REG): Found invariant usage: 1 item

‎llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll‎

Lines changed: 23 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -22,29 +22,34 @@
2222

2323
define void @add(ptr noalias nocapture readonly %src1, ptr noalias nocapture readonly %src2, i32 signext %size, ptr noalias nocapture writeonly %result) {
2424
; CHECK-LABEL: add
25-
; CHECK-SCALAR: LV(REG): Found max usage: 2 item
25+
; CHECK-SCALAR: LV(REG): VF = 1
26+
; CHECK-SCALAR-NEXT: LV(REG): Found max usage: 2 item
2627
; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
2728
; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::FPRRC, 2 registers
2829
; CHECK-SCALAR-NEXT: LV(REG): Found invariant usage: 1 item
2930
; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
30-
; CHECK-LMUL1: LV(REG): Found max usage: 2 item
31+
; CHECK-LMUL1: LV(REG): VF = 2
32+
; CHECK-LMUL1-NEXT: LV(REG): Found max usage: 2 item
3133
; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
3234
; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
3335
; CHECK-LMUL1-NEXT: LV(REG): Found invariant usage: 1 item
3436
; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
35-
; CHECK-LMUL2: LV(REG): Found max usage: 2 item
37+
; CHECK-LMUL2: LV(REG): VF = 4
38+
; CHECK-LMUL2-NEXT: LV(REG): Found max usage: 2 item
3639
; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
37-
; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
40+
; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
3841
; CHECK-LMUL2-NEXT: LV(REG): Found invariant usage: 1 item
3942
; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
40-
; CHECK-LMUL4: LV(REG): Found max usage: 2 item
43+
; CHECK-LMUL4: LV(REG): VF = 8
44+
; CHECK-LMUL4-NEXT: LV(REG): Found max usage: 2 item
4145
; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
42-
; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 8 registers
46+
; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
4347
; CHECK-LMUL4-NEXT: LV(REG): Found invariant usage: 1 item
4448
; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
45-
; CHECK-LMUL8: LV(REG): Found max usage: 2 item
49+
; CHECK-LMUL8: LV(REG): VF = 16
50+
; CHECK-LMUL8-NEXT: LV(REG): Found max usage: 2 item
4651
; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
47-
; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 16 registers
52+
; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 8 registers
4853
; CHECK-LMUL8-NEXT: LV(REG): Found invariant usage: 1 item
4954
; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
5055

@@ -72,18 +77,23 @@ for.body:
7277

7378
define void @goo(ptr nocapture noundef %a, i32 noundef signext %n) {
7479
; CHECK-LABEL: goo
75-
; CHECK-SCALAR: LV(REG): Found max usage: 1 item
80+
; CHECK-SCALAR: LV(REG): VF = 1
81+
; CHECK-SCALAR-NEXT: LV(REG): Found max usage: 1 item
7682
; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
77-
; CHECK-LMUL1: LV(REG): Found max usage: 2 item
83+
; CHECK-LMUL1: LV(REG): VF = 2
84+
; CHECK-LMUL1-NEXT: LV(REG): Found max usage: 2 item
7885
; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers
7986
; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 1 registers
80-
; CHECK-LMUL2: LV(REG): Found max usage: 2 item
87+
; CHECK-LMUL2: LV(REG): VF = 4
88+
; CHECK-LMUL2-NEXT: LV(REG): Found max usage: 2 item
8189
; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers
8290
; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
83-
; CHECK-LMUL4: LV(REG): Found max usage: 2 item
91+
; CHECK-LMUL4: LV(REG): VF = 8
92+
; CHECK-LMUL4-NEXT: LV(REG): Found max usage: 2 item
8493
; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers
8594
; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
86-
; CHECK-LMUL8: LV(REG): Found max usage: 2 item
95+
; CHECK-LMUL8: LV(REG): VF = 16
96+
; CHECK-LMUL8-NEXT: LV(REG): Found max usage: 2 item
8797
; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers
8898
; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 8 registers
8999
entry:

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