[SelectionDAG] Add more cases for UDIV and SDIV

Ported from ValueTracking.

Author: AZero13

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -5614,14 +5614,29 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
       return true;
     break;
   }
-  case ISD::UDIV:
-  case ISD::SDIV:
+  case ISD::UDIV: {
     // div exact can only produce a zero if the dividend is zero.
-    // TODO: For udiv this is also true if Op1 u<= Op0
     if (Op->getFlags().hasExact())
       return isKnownNeverZero(Op.getOperand(0), Depth + 1);
-    break;
 
+    // If Op0 >= Op1, then the result is at least 1, and therefore not 0.
+    KnownBits Op0 = computeKnownBits(Op.getOperand(0), Depth + 1);
+    KnownBits Op1 = computeKnownBits(Op.getOperand(1), Depth + 1);
+    std::optional<bool> Uge = KnownBits::uge(Op0, Op1);
+    return Uge && *Uge;
+  }
+  case ISD::SDIV: {
+    // div exact can only produce a zero if the dividend is zero.
+    if (Op->getFlags().hasExact())
+      return isKnownNeverZero(Op.getOperand(0), Depth + 1);
+
+    KnownBits Op0 = computeKnownBits(Op.getOperand(0), Depth + 1);
+    KnownBits Op1 = computeKnownBits(Op.getOperand(1), Depth + 1);
+    Op0 = Op0.abs(/*IntMinIsPoison*/ false);
+    Op1 = Op1.abs(/*IntMinIsPoison*/ false);
+    std::optional<bool> Uge = KnownBits::uge(Op0, Op1);
+    return Uge && *Uge;
+  }
   case ISD::ADD:
     if (Op->getFlags().hasNoUnsignedWrap())
       if (isKnownNeverZero(Op.getOperand(1), Depth + 1) ||