@@ -666,22 +666,22 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
666666 case RISCVVector::BI__builtin_rvv_vaeskf2_vi_tu:
667667 case RISCVVector::BI__builtin_rvv_vaeskf2_vi:
668668 case RISCVVector::BI__builtin_rvv_vsm4k_vi_tu: {
669- QualType Op1Type = TheCall->getArg (0 )->getType ();
670- QualType Op2Type = TheCall->getArg (1 )->getType ();
671- return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op1Type , 128 ) ||
672- CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op2Type , 128 ) ||
669+ QualType Arg0Type = TheCall->getArg (0 )->getType ();
670+ QualType Arg1Type = TheCall->getArg (1 )->getType ();
671+ return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg0Type , 128 ) ||
672+ CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg1Type , 128 ) ||
673673 SemaRef.BuiltinConstantArgRange (TheCall, 2 , 0 , 31 );
674674 }
675675 case RISCVVector::BI__builtin_rvv_vsm3c_vi_tu:
676676 case RISCVVector::BI__builtin_rvv_vsm3c_vi: {
677- QualType Op1Type = TheCall->getArg (0 )->getType ();
678- return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op1Type , 256 ) ||
677+ QualType Arg0Type = TheCall->getArg (0 )->getType ();
678+ return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg0Type , 256 ) ||
679679 SemaRef.BuiltinConstantArgRange (TheCall, 2 , 0 , 31 );
680680 }
681681 case RISCVVector::BI__builtin_rvv_vaeskf1_vi:
682682 case RISCVVector::BI__builtin_rvv_vsm4k_vi: {
683- QualType Op1Type = TheCall->getArg (0 )->getType ();
684- return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op1Type , 128 ) ||
683+ QualType Arg0Type = TheCall->getArg (0 )->getType ();
684+ return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg0Type , 128 ) ||
685685 SemaRef.BuiltinConstantArgRange (TheCall, 1 , 0 , 31 );
686686 }
687687 case RISCVVector::BI__builtin_rvv_vaesdf_vv:
@@ -706,33 +706,34 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
706706 case RISCVVector::BI__builtin_rvv_vaesz_vs_tu:
707707 case RISCVVector::BI__builtin_rvv_vsm4r_vv_tu:
708708 case RISCVVector::BI__builtin_rvv_vsm4r_vs_tu: {
709- QualType Op1Type = TheCall->getArg (0 )->getType ();
710- QualType Op2Type = TheCall->getArg (1 )->getType ();
711- return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op1Type , 128 ) ||
712- CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op2Type , 128 );
709+ QualType Arg0Type = TheCall->getArg (0 )->getType ();
710+ QualType Arg1Type = TheCall->getArg (1 )->getType ();
711+ return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg0Type , 128 ) ||
712+ CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg1Type , 128 );
713713 }
714714 case RISCVVector::BI__builtin_rvv_vsha2ch_vv:
715715 case RISCVVector::BI__builtin_rvv_vsha2cl_vv:
716716 case RISCVVector::BI__builtin_rvv_vsha2ms_vv:
717717 case RISCVVector::BI__builtin_rvv_vsha2ch_vv_tu:
718718 case RISCVVector::BI__builtin_rvv_vsha2cl_vv_tu:
719719 case RISCVVector::BI__builtin_rvv_vsha2ms_vv_tu: {
720- QualType Op1Type = TheCall->getArg (0 )->getType ();
721- QualType Op2Type = TheCall->getArg (1 )->getType ();
722- QualType Op3Type = TheCall->getArg (2 )->getType ();
720+ QualType Arg0Type = TheCall->getArg (0 )->getType ();
721+ QualType Arg1Type = TheCall->getArg (1 )->getType ();
722+ QualType Arg2Type = TheCall->getArg (2 )->getType ();
723723 ASTContext::BuiltinVectorTypeInfo Info =
724- Context.getBuiltinVectorTypeInfo (Op1Type ->castAs <BuiltinType>());
724+ Context.getBuiltinVectorTypeInfo (Arg0Type ->castAs <BuiltinType>());
725725 uint64_t ElemSize = Context.getTypeSize (Info.ElementType );
726726 if (ElemSize == 64 && !TI.hasFeature (" zvknhb" ))
727727 return Diag (TheCall->getBeginLoc (),
728728 diag::err_riscv_builtin_requires_extension)
729729 << /* IsExtension */ true << TheCall->getSourceRange () << " zvknhb" ;
730730
731- return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op1Type ,
731+ return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg0Type ,
732732 ElemSize * 4 ) ||
733- CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op2Type ,
733+ CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg1Type ,
734734 ElemSize * 4 ) ||
735- CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op3Type, ElemSize * 4 );
735+ CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg2Type,
736+ ElemSize * 4 );
736737 }
737738
738739 case RISCVVector::BI__builtin_rvv_sf_vc_i_se:
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