@@ -2137,7 +2137,8 @@ bool SPIRVInstructionSelector::selectWaveActiveCountBits(
21372137
21382138bool SPIRVInstructionSelector::selectWaveReduceMax (Register ResVReg,
21392139 const SPIRVType *ResType,
2140- MachineInstr &I, bool IsUnsigned) const {
2140+ MachineInstr &I,
2141+ bool IsUnsigned) const {
21412142 assert (I.getNumOperands () == 3 );
21422143 assert (I.getOperand (2 ).isReg ());
21432144 MachineBasicBlock &BB = *I.getParent ();
@@ -2150,9 +2151,9 @@ bool SPIRVInstructionSelector::selectWaveReduceMax(Register ResVReg,
21502151 SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType (32 , I, TII);
21512152 // Retreive the operation to use based on input type
21522153 bool IsFloatTy = GR.isScalarOrVectorOfType (InputRegister, SPIRV::OpTypeFloat);
2153- auto IntegerOpcodeType = IsUnsigned ? SPIRV::OpGroupNonUniformUMax : SPIRV::OpGroupNonUniformSMax;
2154- auto Opcode =
2155- IsFloatTy ? SPIRV::OpGroupNonUniformFMax : IntegerOpcodeType;
2154+ auto IntegerOpcodeType =
2155+ IsUnsigned ? SPIRV::OpGroupNonUniformUMax : SPIRV::OpGroupNonUniformSMax;
2156+ auto Opcode = IsFloatTy ? SPIRV::OpGroupNonUniformFMax : IntegerOpcodeType;
21562157 return BuildMI (BB, I, I.getDebugLoc (), TII.get (Opcode))
21572158 .addDef (ResVReg)
21582159 .addUse (GR.getSPIRVTypeID (ResType))
@@ -3116,9 +3117,9 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
31163117 case Intrinsic::spv_wave_is_first_lane:
31173118 return selectWaveOpInst (ResVReg, ResType, I, SPIRV::OpGroupNonUniformElect);
31183119 case Intrinsic::spv_wave_reduce_umax:
3119- return selectWaveReduceMax (ResVReg, ResType, I, /* IsUnsigned*/ true );
3120+ return selectWaveReduceMax (ResVReg, ResType, I, /* IsUnsigned*/ true );
31203121 case Intrinsic::spv_wave_reduce_max:
3121- return selectWaveReduceMax (ResVReg, ResType, I, /* IsUnsigned*/ false );
3122+ return selectWaveReduceMax (ResVReg, ResType, I, /* IsUnsigned*/ false );
31223123 case Intrinsic::spv_wave_reduce_sum:
31233124 return selectWaveReduceSum (ResVReg, ResType, I);
31243125 case Intrinsic::spv_wave_readlane:
0 commit comments