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Remove UnsafeFPMath in visitFADDForFMACombine 
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5 files changed

+27
-30
lines changed

5 files changed

+27
-30
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -17030,8 +17030,7 @@ SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) {
1703017030
// fadd (G, (fma A, B, (fma (C, D, (fmul (E, F)))))) -->
1703117031
// fma A, B, (fma C, D, fma (E, F, G)).
1703217032
// This requires reassociation because it changes the order of operations.
17033-
bool CanReassociate =
17034-
Options.UnsafeFPMath || N->getFlags().hasAllowReassociation();
17033+
bool CanReassociate = N->getFlags().hasAllowReassociation();
1703517034
if (CanReassociate) {
1703617035
SDValue FMA, E;
1703717036
if (isFusedOp(N0) && N0.hasOneUse()) {
@@ -18227,8 +18226,7 @@ template <class MatchContextClass> SDValue DAGCombiner::visitFMA(SDNode *N) {
1822718226
!DAG.isConstantFPBuildVectorOrConstantFP(N1))
1822818227
return matcher.getNode(ISD::FMA, DL, VT, N1, N0, N2);
1822918228

18230-
bool CanReassociate =
18231-
Options.UnsafeFPMath || N->getFlags().hasAllowReassociation();
18229+
bool CanReassociate = N->getFlags().hasAllowReassociation();
1823218230
if (CanReassociate) {
1823318231
// (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
1823418232
if (matcher.match(N2, ISD::FMUL) && N0 == N2.getOperand(0) &&

‎llvm/test/CodeGen/ARM/fp-fast.ll‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,12 @@
1-
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 -mattr=+vfp4 -enable-unsafe-fp-math %s -o - \
2-
; RUN: | FileCheck %s
1+
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 -mattr=+vfp4 %s -o - | FileCheck %s
32

43
; CHECK: test1
54
define float @test1(float %x) {
65
; CHECK-NOT: vfma
76
; CHECK: vmul.f32
87
; CHECK-NOT: vfma
98
%t1 = fmul float %x, 3.0
10-
%t2 = call float @llvm.fma.f32(float %x, float 2.0, float %t1)
9+
%t2 = call reassoc float @llvm.fma.f32(float %x, float 2.0, float %t1)
1110
ret float %t2
1211
}
1312

@@ -17,7 +16,7 @@ define float @test2(float %x, float %y) {
1716
; CHECK: vfma.f32
1817
; CHECK-NOT: vmul
1918
%t1 = fmul float %x, 3.0
20-
%t2 = call float @llvm.fma.f32(float %t1, float 2.0, float %y)
19+
%t2 = call reassoc float @llvm.fma.f32(float %t1, float 2.0, float %y)
2120
ret float %t2
2221
}
2322

@@ -44,7 +43,7 @@ define float @test5(float %x) {
4443
; CHECK-NOT: vfma
4544
; CHECK: vmul.f32
4645
; CHECK-NOT: vfma
47-
%t2 = call float @llvm.fma.f32(float %x, float 2.0, float %x)
46+
%t2 = call reassoc float @llvm.fma.f32(float %x, float 2.0, float %x)
4847
ret float %t2
4948
}
5049

@@ -54,7 +53,7 @@ define float @test6(float %x) {
5453
; CHECK: vmul.f32
5554
; CHECK-NOT: vfma
5655
%t1 = fsub float -0.0, %x
57-
%t2 = call float @llvm.fma.f32(float %x, float 5.0, float %t1)
56+
%t2 = call reassoc float @llvm.fma.f32(float %x, float 5.0, float %t1)
5857
ret float %t2
5958
}
6059

‎llvm/test/CodeGen/NVPTX/fma-assoc.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -20,10 +20,10 @@ define ptx_device float @t1_f32(float %x, float %y, float %z,
2020
; CHECK-UNSAFE-NEXT: st.param.b32 [func_retval0], %r7;
2121
; CHECK-UNSAFE-NEXT: ret;
2222
float %u, float %v) {
23-
%a = fmul float %x, %y
24-
%b = fmul float %u, %v
25-
%c = fadd float %a, %b
26-
%d = fadd float %c, %z
23+
%a = fmul reassoc float %x, %y
24+
%b = fmul reassoc float %u, %v
25+
%c = fadd reassoc float %a, %b
26+
%d = fadd reassoc float %c, %z
2727
ret float %d
2828
}
2929

@@ -43,10 +43,10 @@ define ptx_device double @t1_f64(double %x, double %y, double %z,
4343
; CHECK-UNSAFE-NEXT: st.param.b64 [func_retval0], %rd7;
4444
; CHECK-UNSAFE-NEXT: ret;
4545
double %u, double %v) {
46-
%a = fmul double %x, %y
47-
%b = fmul double %u, %v
48-
%c = fadd double %a, %b
49-
%d = fadd double %c, %z
46+
%a = fmul reassoc double %x, %y
47+
%b = fmul reassoc double %u, %v
48+
%c = fadd reassoc double %a, %b
49+
%d = fadd reassoc double %c, %z
5050
ret double %d
5151
}
5252

‎llvm/test/CodeGen/X86/fma_patterns.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1672,9 +1672,9 @@ define <4 x float> @test_v4f32_fma_x_c1_fmul_x_c2(<4 x float> %x) #0 {
16721672
; AVX512: # %bb.0:
16731673
; AVX512-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
16741674
; AVX512-NEXT: retq
1675-
%m0 = fmul <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
1676-
%m1 = fmul <4 x float> %x, <float 4.0, float 3.0, float 2.0, float 1.0>
1677-
%a = fadd <4 x float> %m0, %m1
1675+
%m0 = fmul contract reassoc <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
1676+
%m1 = fmul contract reassoc <4 x float> %x, <float 4.0, float 3.0, float 2.0, float 1.0>
1677+
%a = fadd contract reassoc <4 x float> %m0, %m1
16781678
ret <4 x float> %a
16791679
}
16801680

@@ -1697,9 +1697,9 @@ define <4 x float> @test_v4f32_fma_fmul_x_c1_c2_y(<4 x float> %x, <4 x float> %y
16971697
; AVX512: # %bb.0:
16981698
; AVX512-NEXT: vfmadd132ps {{.*#+}} xmm0 = (xmm0 * mem) + xmm1
16991699
; AVX512-NEXT: retq
1700-
%m0 = fmul <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
1701-
%m1 = fmul <4 x float> %m0, <float 4.0, float 3.0, float 2.0, float 1.0>
1702-
%a = fadd <4 x float> %m1, %y
1700+
%m0 = fmul contract reassoc <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
1701+
%m1 = fmul contract reassoc <4 x float> %m0, <float 4.0, float 3.0, float 2.0, float 1.0>
1702+
%a = fadd contract reassoc <4 x float> %m1, %y
17031703
ret <4 x float> %a
17041704
}
17051705

‎llvm/test/CodeGen/X86/fma_patterns_wide.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1053,9 +1053,9 @@ define <16 x float> @test_v16f32_fma_x_c1_fmul_x_c2(<16 x float> %x) #0 {
10531053
; AVX512: # %bb.0:
10541054
; AVX512-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
10551055
; AVX512-NEXT: retq
1056-
%m0 = fmul <16 x float> %x, <float 17.0, float 16.0, float 15.0, float 14.0, float 13.0, float 12.0, float 11.0, float 10.0, float 9.0, float 8.0, float 7.0, float 6.0, float 5.0, float 4.0, float 3.0, float 2.0>
1057-
%m1 = fmul <16 x float> %x, <float 16.0, float 15.0, float 14.0, float 13.0, float 12.0, float 11.0, float 10.0, float 9.0, float 8.0, float 7.0, float 6.0, float 5.0, float 4.0, float 3.0, float 2.0, float 1.0>
1058-
%a = fadd <16 x float> %m0, %m1
1056+
%m0 = fmul contract reassoc <16 x float> %x, <float 17.0, float 16.0, float 15.0, float 14.0, float 13.0, float 12.0, float 11.0, float 10.0, float 9.0, float 8.0, float 7.0, float 6.0, float 5.0, float 4.0, float 3.0, float 2.0>
1057+
%m1 = fmul contract reassoc <16 x float> %x, <float 16.0, float 15.0, float 14.0, float 13.0, float 12.0, float 11.0, float 10.0, float 9.0, float 8.0, float 7.0, float 6.0, float 5.0, float 4.0, float 3.0, float 2.0, float 1.0>
1058+
%a = fadd contract reassoc <16 x float> %m0, %m1
10591059
ret <16 x float> %a
10601060
}
10611061

@@ -1080,9 +1080,9 @@ define <16 x float> @test_v16f32_fma_fmul_x_c1_c2_y(<16 x float> %x, <16 x float
10801080
; AVX512: # %bb.0:
10811081
; AVX512-NEXT: vfmadd132ps {{.*#+}} zmm0 = (zmm0 * mem) + zmm1
10821082
; AVX512-NEXT: retq
1083-
%m0 = fmul <16 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>
1084-
%m1 = fmul <16 x float> %m0, <float 16.0, float 15.0, float 14.0, float 13.0, float 12.0, float 11.0, float 10.0, float 9.0, float 8.0, float 7.0, float 6.0, float 5.0, float 4.0, float 3.0, float 2.0, float 1.0>
1085-
%a = fadd <16 x float> %m1, %y
1083+
%m0 = fmul contract reassoc <16 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>
1084+
%m1 = fmul contract reassoc <16 x float> %m0, <float 16.0, float 15.0, float 14.0, float 13.0, float 12.0, float 11.0, float 10.0, float 9.0, float 8.0, float 7.0, float 6.0, float 5.0, float 4.0, float 3.0, float 2.0, float 1.0>
1085+
%a = fadd contract reassoc <16 x float> %m1, %y
10861086
ret <16 x float> %a
10871087
}
10881088

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