One more

Author: AZero13

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -7454,6 +7454,19 @@ SDValue AArch64TargetLowering::LowerABD(SDValue Op, SelectionDAG &DAG) const {
   SDValue RHS = Op.getOperand(1);
   SDLoc DL(Op);
 
+  if (!isa<ConstantSDNode>(RHS) || !isLegalCmpImmed(RHS->getAsAPIntVal())) {
+    SDValue TheLHS = isCMN(LHS, IsSigned ? ISD::SETGE : ISD::SETUGE, DAG)
+                         ? LHS.getOperand(1)
+                         : LHS;
+    SDValue TheRHS = isCMN(RHS, IsSigned ? ISD::SETGE : ISD::SETUGE, DAG)
+                         ? RHS.getOperand(1)
+                         : RHS;
+    if (getCmpOperandFoldingProfit(TheLHS) >
+        getCmpOperandFoldingProfit(TheRHS)) {
+      std::swap(LHS, RHS);
+    }
+  }
+
   // If the subtract doesn't overflow then just use abs(sub())
   bool IsNonNegative = DAG.SignBitIsZero(LHS) && DAG.SignBitIsZero(RHS);
 

llvm/test/CodeGen/AArch64/abds-neg.ll

@@ -72,8 +72,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
 define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
 ; CHECK-LABEL: abd_ext_i16_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth w8, w0
-; CHECK-NEXT:    subs w8, w8, w1
+; CHECK-NEXT:    subs w8, w1, w0, sxth
 ; CHECK-NEXT:    cneg w0, w8, ge
 ; CHECK-NEXT:    ret
   %aext = sext i16 %a to i64

llvm/test/CodeGen/AArch64/abds.ll

@@ -68,8 +68,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
 define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
 ; CHECK-LABEL: abd_ext_i16_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxth w8, w0
-; CHECK-NEXT:    subs w8, w8, w1
+; CHECK-NEXT:    subs w8, w1, w0, sxth
 ; CHECK-NEXT:    cneg w0, w8, lt
 ; CHECK-NEXT:    ret
   %aext = sext i16 %a to i64
@@ -498,10 +497,7 @@ define i64 @vector_legalized(i16 %a, i16 %b) {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sxth w8, w0
 ; CHECK-NEXT:    subs w8, w8, w1, sxth
-; CHECK-NEXT:    addp d0, v0.2d
-; CHECK-NEXT:    cneg w8, w8, mi
-; CHECK-NEXT:    fmov x9, d0
-; CHECK-NEXT:    add x0, x9, x8
+; CHECK-NEXT:    cneg w0, w8, mi
 ; CHECK-NEXT:    ret
   %ea = sext i16 %a to i32
   %eb = sext i16 %b to i32

llvm/test/CodeGen/AArch64/abdu-neg.ll

@@ -72,8 +72,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
 define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
 ; CHECK-LABEL: abd_ext_i16_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    and w8, w0, #0xffff
-; CHECK-NEXT:    subs w8, w8, w1
+; CHECK-NEXT:    subs w8, w1, w0, uxth
 ; CHECK-NEXT:    cneg w0, w8, hs
 ; CHECK-NEXT:    ret
   %aext = zext i16 %a to i64

llvm/test/CodeGen/AArch64/abdu.ll

@@ -68,8 +68,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
 define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
 ; CHECK-LABEL: abd_ext_i16_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    and w8, w0, #0xffff
-; CHECK-NEXT:    subs w8, w8, w1
+; CHECK-NEXT:    subs w8, w1, w0, uxth
 ; CHECK-NEXT:    cneg w0, w8, lo
 ; CHECK-NEXT:    ret
   %aext = zext i16 %a to i64
@@ -363,10 +362,7 @@ define i64 @vector_legalized(i16 %a, i16 %b) {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0xffff
 ; CHECK-NEXT:    subs w8, w8, w1, uxth
-; CHECK-NEXT:    cneg w8, w8, mi
-; CHECK-NEXT:    addp d0, v0.2d
-; CHECK-NEXT:    fmov x9, d0
-; CHECK-NEXT:    add x0, x9, x8
+; CHECK-NEXT:    cneg w0, w8, mi
 ; CHECK-NEXT:    ret
   %ea = zext i16 %a to i32
   %eb = zext i16 %b to i32