[RISCV] Add copies to physical registers in VL optimizer tests. NFC (#151170)

In an upcoming patch to support recurrences in the RISCVVLOptimizer, we
need to perform an optimistic dataflow analysis where we assume
instructions have a DemandedVL of zero until a user is encountered.

Because of this if there's no "root" instruction, nothing will be
demanded and all the VLs will be set to zero.

This prepares for this by adding a copy to a physical register in the
MIR tests so that the behaviour is preserved, and matches whats
generated lowering from regular LLVM IR.

Author: lukel97